| developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #include <config.h> |
| 9 | #include <asm-offsets.h> |
| 10 | #include <asm/cacheops.h> |
| 11 | #include <asm/regdef.h> |
| 12 | #include <asm/mipsregs.h> |
| 13 | #include <asm/addrspace.h> |
| 14 | #include <asm/asm.h> |
| 15 | #include "mt7628.h" |
| 16 | |
| 17 | /* Set temporary stack address range */ |
| 18 | #ifndef CONFIG_SYS_INIT_SP_ADDR |
| 19 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 20 | CONFIG_SYS_INIT_SP_OFFSET) |
| 21 | #endif |
| 22 | |
| 23 | #define CACHE_STACK_SIZE 0x4000 |
| 24 | #define CACHE_STACK_BASE (CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE) |
| 25 | |
| 26 | #define DELAY_USEC(us) ((58 * (us)) / 3) |
| 27 | |
| 28 | .set noreorder |
| 29 | |
| 30 | LEAF(mips_sram_init) |
| Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 31 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
| developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 32 | /* Setup CPU PLL */ |
| 33 | li t0, DELAY_USEC(1000000) |
| 34 | li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG) |
| 35 | li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG) |
| 36 | |
| 37 | _check_rom_status: |
| 38 | lw t3, 0(t1) |
| 39 | andi t3, t3, 1 |
| 40 | bnez t3, _rom_normal |
| 41 | subu t0, t0, 1 |
| 42 | bnez t0, _check_rom_status |
| 43 | nop |
| 44 | |
| 45 | lw t3, 0(t2) |
| 46 | ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL) |
| 47 | xori t3, CPU_PLL_FROM_BBP |
| 48 | b _cpu_pll_done |
| 49 | nop |
| 50 | |
| 51 | _rom_normal: |
| 52 | lw t3, 0(t2) |
| 53 | ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL | \ |
| 54 | DIS_BBP_SLEEP | EN_BBP_CLK) |
| 55 | xori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL) |
| 56 | |
| 57 | _cpu_pll_done: |
| 58 | sw t3, 0(t2) |
| 59 | |
| 60 | li t2, KSEG1ADDR(RBUSCTL_BASE + RBUSCTL_DYN_CFG0_REG) |
| 61 | lw t3, 0(t2) |
| 62 | ori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M) |
| 63 | xori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M) |
| 64 | ori t3, t3, ((1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S)) |
| 65 | sw t3, 0(t2) |
| 66 | |
| 67 | /* Clear WST & SPR bits in ErrCtl */ |
| 68 | mfc0 t0, CP0_ECC |
| 69 | ins t0, zero, 30, 2 |
| 70 | mtc0 t0, CP0_ECC |
| 71 | ehb |
| 72 | |
| 73 | /* Simply initialize I-Cache */ |
| 74 | li a0, 0 |
| 75 | li a1, CONFIG_SYS_ICACHE_SIZE |
| 76 | |
| 77 | mtc0 zero, CP0_TAGLO /* Zero to DDataLo */ |
| 78 | |
| 79 | 1: cache INDEX_STORE_TAG_I, 0(a0) |
| 80 | addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE |
| 81 | bne a0, a1, 1b |
| 82 | nop |
| 83 | |
| 84 | /* Simply initialize D-Cache */ |
| 85 | li a0, 0 |
| 86 | li a1, CONFIG_SYS_DCACHE_SIZE |
| 87 | |
| 88 | mtc0 zero, CP0_TAGLO, 2 |
| 89 | |
| 90 | 2: cache INDEX_STORE_TAG_D, 0(a0) |
| 91 | addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE |
| 92 | bne a0, a1, 2b |
| 93 | nop |
| 94 | |
| 95 | /* Set KSEG0 Cachable */ |
| 96 | mfc0 t0, CP0_CONFIG |
| 97 | and t0, t0, MIPS_CONF_IMPL |
| 98 | or t0, t0, CONF_CM_CACHABLE_NONCOHERENT |
| 99 | mtc0 t0, CP0_CONFIG |
| 100 | ehb |
| 101 | |
| 102 | /* Lock D-Cache */ |
| 103 | PTR_LI a0, CACHE_STACK_BASE /* D-Cache lock base */ |
| 104 | li a1, CACHE_STACK_SIZE /* D-Cache lock size */ |
| 105 | li a2, 0x1ffff800 /* Mask of DTagLo[PTagLo] */ |
| 106 | |
| 107 | 3: |
| 108 | /* Lock one cacheline */ |
| 109 | and t0, a0, a2 |
| 110 | ori t0, 0xe0 /* Valid & Dirty & Lock bits */ |
| 111 | mtc0 t0, CP0_TAGLO, 2 /* Write to DTagLo */ |
| 112 | ehb |
| 113 | cache INDEX_STORE_TAG_D, 0(a0) |
| 114 | |
| 115 | addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE |
| 116 | sub a1, CONFIG_SYS_DCACHE_LINE_SIZE |
| 117 | bnez a1, 3b |
| 118 | nop |
| Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 119 | #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |
| developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 120 | |
| 121 | jr ra |
| 122 | nop |
| 123 | END(mips_sram_init) |
| 124 | |
| 125 | NESTED(lowlevel_init, 0, ra) |
| 126 | /* Save ra and do real lowlevel initialization */ |
| 127 | move s0, ra |
| 128 | |
| 129 | PTR_LA t9, mt7628_init |
| 130 | jalr t9 |
| 131 | nop |
| 132 | |
| 133 | move ra, s0 |
| 134 | |
| 135 | #if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) |
| 136 | /* Set malloc base */ |
| 137 | li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15) |
| 138 | PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset |
| 139 | #endif |
| 140 | |
| 141 | /* Write back data in locked cache to DRAM */ |
| 142 | PTR_LI a0, CACHE_STACK_BASE /* D-Cache unlock base */ |
| 143 | li a1, CACHE_STACK_SIZE /* D-Cache unlock size */ |
| 144 | |
| 145 | 1: |
| 146 | cache HIT_WRITEBACK_INV_D, 0(a0) |
| 147 | addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE |
| 148 | sub a1, CONFIG_SYS_DCACHE_LINE_SIZE |
| 149 | bnez a1, 1b |
| 150 | nop |
| 151 | |
| 152 | /* Set KSEG0 Uncached */ |
| 153 | mfc0 t0, CP0_CONFIG |
| 154 | and t0, t0, MIPS_CONF_IMPL |
| 155 | or t0, t0, CONF_CM_UNCACHED |
| 156 | mtc0 t0, CP0_CONFIG |
| 157 | ehb |
| 158 | |
| 159 | jr ra |
| 160 | nop |
| 161 | END(lowlevel_init) |