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git01.mediatek.com / filogic / uboot / 9d6eeef72b3eb961cb3a7b4223970aebbaec5b7f / . / include / ppc405.h
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wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21
22#ifndef __PPC405_H__
23#define __PPC405_H__
24
25/*--------------------------------------------------------------------- */
26/* Special Purpose Registers */
27/*--------------------------------------------------------------------- */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]28 #define srr2 0x3de /* save/restore register 2 */
29 #define srr3 0x3df /* save/restore register 3 */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]30 #define dbsr 0x3f0 /* debug status register */
31 #define dbcr0 0x3f2 /* debug control register 0 */
32 #define dbcr1 0x3bd /* debug control register 1 */
33 #define iac1 0x3f4 /* instruction address comparator 1 */
34 #define iac2 0x3f5 /* instruction address comparator 2 */
35 #define iac3 0x3b4 /* instruction address comparator 3 */
36 #define iac4 0x3b5 /* instruction address comparator 4 */
37 #define dac1 0x3f6 /* data address comparator 1 */
38 #define dac2 0x3f7 /* data address comparator 2 */
39 #define dccr 0x3fa /* data cache control register */
40 #define iccr 0x3fb /* instruction cache control register */
41 #define esr 0x3d4 /* execption syndrome register */
42 #define dear 0x3d5 /* data exeption address register */
43 #define evpr 0x3d6 /* exeption vector prefix register */
44 #define tsr 0x3d8 /* timer status register */
45 #define tcr 0x3da /* timer control register */
46 #define pit 0x3db /* programmable interval timer */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]47 #define sgr 0x3b9 /* storage guarded reg */
48 #define dcwr 0x3ba /* data cache write-thru reg*/
49 #define sler 0x3bb /* storage little-endian reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]50 #define cdbcr 0x3d7 /* cache debug cntrl reg */
51 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
52 #define ccr0 0x3b3 /* core configuration register */
53 #define dvc1 0x3b6 /* data value compare register 1 */
54 #define dvc2 0x3b7 /* data value compare register 2 */
55 #define pid 0x3b1 /* process ID */
56 #define su0r 0x3bc /* storage user-defined register 0 */
57 #define zpr 0x3b0 /* zone protection regsiter */
58
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]59 #define tbl 0x11c /* time base lower - privileged write */
60 #define tbu 0x11d /* time base upper - privileged write */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]61
62 #define sprg4r 0x104 /* Special purpose general 4 - read only */
63 #define sprg5r 0x105 /* Special purpose general 5 - read only */
64 #define sprg6r 0x106 /* Special purpose general 6 - read only */
65 #define sprg7r 0x107 /* Special purpose general 7 - read only */
66 #define sprg4w 0x114 /* Special purpose general 4 - write only */
67 #define sprg5w 0x115 /* Special purpose general 5 - write only */
68 #define sprg6w 0x116 /* Special purpose general 6 - write only */
69 #define sprg7w 0x117 /* Special purpose general 7 - write only */
70
71/******************************************************************************
72 * Special for PPC405GP
73 ******************************************************************************/
74
75/******************************************************************************
76 * DMA
77 ******************************************************************************/
78#define DMA_DCR_BASE 0x100
79#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
80#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
81#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
82#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
83#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
84#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
85#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
86#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
87#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
88#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
89#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
90#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
91#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
92#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
93#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
94#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
95#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
96#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
97#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
98#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
99#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
100#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
101#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
102
103/******************************************************************************
104 * Universal interrupt controller
105 ******************************************************************************/
106#define UIC_DCR_BASE 0xc0
107#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
108#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
109#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
110#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
111#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
112#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
113#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
114#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
115#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
116
117/*-----------------------------------------------------------------------------+
118| Universal interrupt controller interrupts
119+-----------------------------------------------------------------------------*/
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]120#if defined(CONFIG_405EZ)
121#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
122#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
123#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
124#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
125#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
126#define UIC_UART0 0x04000000 /* UART 0 */
127#define UIC_UART1 0x02000000 /* UART 1 */
128#define UIC_CAN0 0x01000000 /* CAN 0 */
129#define UIC_CAN1 0x00800000 /* CAN 1 */
130#define UIC_SPI 0x00400000 /* SPI */
131#define UIC_IIC 0x00200000 /* IIC */
132#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
133#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
134#define UIC_USBH1 0x00040000 /* USB Host 1 */
135#define UIC_USBH2 0x00020000 /* USB Host 2 */
136#define UIC_USBDEV 0x00010000 /* USB Device */
137#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
138#define UIC_ENET1 0x00008000 /* dummy define */
139#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
140
141#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
142#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
143#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
144#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
145
146#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
147#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
148#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
149#define UIC_NAND 0x00000200 /* NAND Flash controller */
150#define UIC_ADC 0x00000100 /* ADC */
151#define UIC_DAC 0x00000080 /* DAC */
152#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
153#define UIC_RESERVED0 0x00000020 /* Reserved */
154#define UIC_EXT0 0x00000010 /* External interrupt 0 */
155#define UIC_EXT1 0x00000008 /* External interrupt 1 */
156#define UIC_EXT2 0x00000004 /* External interrupt 2 */
157#define UIC_EXT3 0x00000002 /* External interrupt 3 */
158#define UIC_EXT4 0x00000001 /* External interrupt 4 */
159
160#else /* !defined(CONFIG_405EZ) */
161
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]162#define UIC_UART0 0x80000000 /* UART 0 */
163#define UIC_UART1 0x40000000 /* UART 1 */
164#define UIC_IIC 0x20000000 /* IIC */
165#define UIC_EXT_MAST 0x10000000 /* External Master */
166#define UIC_PCI 0x08000000 /* PCI write to command reg */
167#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
168#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
169#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
170#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
171#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
172#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
173#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
174#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
175#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
176#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
wdenk2a6109c2004-06-06 23:53:59 +0000[diff] [blame]177#define UIC_ENET 0x00010000 /* Ethernet0 */
178#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
179#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]180#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]181#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
182#define UIC_EXT0 0x00000040 /* External interrupt 0 */
183#define UIC_EXT1 0x00000020 /* External interrupt 1 */
184#define UIC_EXT2 0x00000010 /* External interrupt 2 */
185#define UIC_EXT3 0x00000008 /* External interrupt 3 */
186#define UIC_EXT4 0x00000004 /* External interrupt 4 */
187#define UIC_EXT5 0x00000002 /* External interrupt 5 */
188#define UIC_EXT6 0x00000001 /* External interrupt 6 */
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]189#endif /* defined(CONFIG_405EZ) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]190
191/******************************************************************************
192 * SDRAM Controller
193 ******************************************************************************/
194#define SDRAM_DCR_BASE 0x10
195#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
196#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
197 /* values for memcfga register - indirect addressing of these regs */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]198#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]199 #define mem_besra 0x00 /* bus error syndrome reg a */
200 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
201 #define mem_besrb 0x08 /* bus error syndrome reg b */
202 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
203 #define mem_bear 0x10 /* bus error address reg */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]204#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]205 #define mem_mcopt1 0x20 /* memory controller options 1 */
Heiko Schocher3c58a992007-01-11 15:44:44 +0100[diff] [blame]206 #define mem_status 0x24 /* memory status */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]207 #define mem_rtr 0x30 /* refresh timer reg */
208 #define mem_pmit 0x34 /* power management idle timer */
209 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
210 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]211#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]212 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
213 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]214#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]215 #define mem_sdtr1 0x80 /* timing reg 1 */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]216#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]217 #define mem_ecccf 0x94 /* ECC configuration */
218 #define mem_eccerr 0x98 /* ECC error status */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]219#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]220
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]221#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]222/******************************************************************************
223 * Decompression Controller
224 ******************************************************************************/
225#define DECOMP_DCR_BASE 0x14
226#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
227#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
228 /* values for kiar register - indirect addressing of these regs */
229 #define kitor0 0x00 /* index table origin register 0 */
230 #define kitor1 0x01 /* index table origin register 1 */
231 #define kitor2 0x02 /* index table origin register 2 */
232 #define kitor3 0x03 /* index table origin register 3 */
233 #define kaddr0 0x04 /* address decode definition regsiter 0 */
234 #define kaddr1 0x05 /* address decode definition regsiter 1 */
235 #define kconf 0x40 /* decompression core config register */
236 #define kid 0x41 /* decompression core ID register */
237 #define kver 0x42 /* decompression core version # reg */
238 #define kpear 0x50 /* bus error addr reg (PLB addr) */
239 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
240 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
241 #define kesr0s 0x53 /* bus error status reg 0 (set) */
242 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
243 /* Only the first one is given here. */
244 #define krom0 0x400 /* SRAM/ROM read/write */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]245#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]246
247/******************************************************************************
248 * Power Management
249 ******************************************************************************/
250#define POWERMAN_DCR_BASE 0xb8
251#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
252#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
253#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
254
255/******************************************************************************
256 * Extrnal Bus Controller
257 ******************************************************************************/
258#define EBC_DCR_BASE 0x12
259#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
260#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
261 /* values for ebccfga register - indirect addressing of these regs */
262 #define pb0cr 0x00 /* periph bank 0 config reg */
263 #define pb1cr 0x01 /* periph bank 1 config reg */
264 #define pb2cr 0x02 /* periph bank 2 config reg */
265 #define pb3cr 0x03 /* periph bank 3 config reg */
266 #define pb4cr 0x04 /* periph bank 4 config reg */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]267#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]268 #define pb5cr 0x05 /* periph bank 5 config reg */
269 #define pb6cr 0x06 /* periph bank 6 config reg */
270 #define pb7cr 0x07 /* periph bank 7 config reg */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]271#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]272 #define pb0ap 0x10 /* periph bank 0 access parameters */
273 #define pb1ap 0x11 /* periph bank 1 access parameters */
274 #define pb2ap 0x12 /* periph bank 2 access parameters */
275 #define pb3ap 0x13 /* periph bank 3 access parameters */
276 #define pb4ap 0x14 /* periph bank 4 access parameters */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]277#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]278 #define pb5ap 0x15 /* periph bank 5 access parameters */
279 #define pb6ap 0x16 /* periph bank 6 access parameters */
280 #define pb7ap 0x17 /* periph bank 7 access parameters */
stroeseb0ca12d2003-12-09 14:59:11 +0000[diff] [blame]281#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]282 #define pbear 0x20 /* periph bus error addr reg */
283 #define pbesr0 0x21 /* periph bus error status reg 0 */
284 #define pbesr1 0x22 /* periph bus error status reg 1 */
285 #define epcr 0x23 /* external periph control reg */
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]286#define EBC0_CFG 0x23 /* external bus configuration reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]287
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]288#ifdef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]289/******************************************************************************
290 * Control
291 ******************************************************************************/
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]292#define CNTRL_DCR_BASE 0x0f0
293#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
294#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
295#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
296#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
297#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
298#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
299
300#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
301#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
302#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
303#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
304#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
305#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
306#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
307#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
308#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
309#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
310
311/* Bit definitions */
312#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
313#define PLLMR0_CPU_DIV_BYPASS 0x00000000
314#define PLLMR0_CPU_DIV_2 0x00100000
315#define PLLMR0_CPU_DIV_3 0x00200000
316#define PLLMR0_CPU_DIV_4 0x00300000
317
318#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
319#define PLLMR0_CPU_PLB_DIV_1 0x00000000
320#define PLLMR0_CPU_PLB_DIV_2 0x00010000
321#define PLLMR0_CPU_PLB_DIV_3 0x00020000
322#define PLLMR0_CPU_PLB_DIV_4 0x00030000
323
324#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
325#define PLLMR0_OPB_PLB_DIV_1 0x00000000
326#define PLLMR0_OPB_PLB_DIV_2 0x00001000
327#define PLLMR0_OPB_PLB_DIV_3 0x00002000
328#define PLLMR0_OPB_PLB_DIV_4 0x00003000
329
330#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
331#define PLLMR0_EXB_PLB_DIV_2 0x00000000
332#define PLLMR0_EXB_PLB_DIV_3 0x00000100
333#define PLLMR0_EXB_PLB_DIV_4 0x00000200
334#define PLLMR0_EXB_PLB_DIV_5 0x00000300
335
336#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
337#define PLLMR0_MAL_PLB_DIV_1 0x00000000
338#define PLLMR0_MAL_PLB_DIV_2 0x00000010
339#define PLLMR0_MAL_PLB_DIV_3 0x00000020
340#define PLLMR0_MAL_PLB_DIV_4 0x00000030
341
342#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
343#define PLLMR0_PCI_PLB_DIV_1 0x00000000
344#define PLLMR0_PCI_PLB_DIV_2 0x00000001
345#define PLLMR0_PCI_PLB_DIV_3 0x00000002
346#define PLLMR0_PCI_PLB_DIV_4 0x00000003
347
348#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
349#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
350#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
351#define PLLMR1_FBMUL_DIV_16 0x00000000
352#define PLLMR1_FBMUL_DIV_1 0x00100000
353#define PLLMR1_FBMUL_DIV_2 0x00200000
354#define PLLMR1_FBMUL_DIV_3 0x00300000
355#define PLLMR1_FBMUL_DIV_4 0x00400000
356#define PLLMR1_FBMUL_DIV_5 0x00500000
357#define PLLMR1_FBMUL_DIV_6 0x00600000
358#define PLLMR1_FBMUL_DIV_7 0x00700000
359#define PLLMR1_FBMUL_DIV_8 0x00800000
360#define PLLMR1_FBMUL_DIV_9 0x00900000
361#define PLLMR1_FBMUL_DIV_10 0x00A00000
362#define PLLMR1_FBMUL_DIV_11 0x00B00000
363#define PLLMR1_FBMUL_DIV_12 0x00C00000
364#define PLLMR1_FBMUL_DIV_13 0x00D00000
365#define PLLMR1_FBMUL_DIV_14 0x00E00000
366#define PLLMR1_FBMUL_DIV_15 0x00F00000
367
368#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
369#define PLLMR1_FWDVA_DIV_8 0x00000000
370#define PLLMR1_FWDVA_DIV_7 0x00010000
371#define PLLMR1_FWDVA_DIV_6 0x00020000
372#define PLLMR1_FWDVA_DIV_5 0x00030000
373#define PLLMR1_FWDVA_DIV_4 0x00040000
374#define PLLMR1_FWDVA_DIV_3 0x00050000
375#define PLLMR1_FWDVA_DIV_2 0x00060000
376#define PLLMR1_FWDVA_DIV_1 0x00070000
377#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
378#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
379
380/* Defines for CPC0_EPRCSR register */
381#define CPC0_EPRCSR_E0NFE 0x80000000
382#define CPC0_EPRCSR_E1NFE 0x40000000
383#define CPC0_EPRCSR_E1RPP 0x00000080
384#define CPC0_EPRCSR_E0RPP 0x00000040
385#define CPC0_EPRCSR_E1ERP 0x00000020
386#define CPC0_EPRCSR_E0ERP 0x00000010
387#define CPC0_EPRCSR_E1PCI 0x00000002
388#define CPC0_EPRCSR_E0PCI 0x00000001
389
390/* Defines for CPC0_PCI Register */
391#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
392#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
393#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
394
395/* Defines for CPC0_BOOR Register */
396#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
397
398/* Defines for CPC0_PLLMR1 Register fields */
399#define PLL_ACTIVE 0x80000000
400#define CPC0_PLLMR1_SSCS 0x80000000
401#define PLL_RESET 0x40000000
402#define CPC0_PLLMR1_PLLR 0x40000000
403 /* Feedback multiplier */
404#define PLL_FBKDIV 0x00F00000
405#define CPC0_PLLMR1_FBDV 0x00F00000
406#define PLL_FBKDIV_16 0x00000000
407#define PLL_FBKDIV_1 0x00100000
408#define PLL_FBKDIV_2 0x00200000
409#define PLL_FBKDIV_3 0x00300000
410#define PLL_FBKDIV_4 0x00400000
411#define PLL_FBKDIV_5 0x00500000
412#define PLL_FBKDIV_6 0x00600000
413#define PLL_FBKDIV_7 0x00700000
414#define PLL_FBKDIV_8 0x00800000
415#define PLL_FBKDIV_9 0x00900000
416#define PLL_FBKDIV_10 0x00A00000
417#define PLL_FBKDIV_11 0x00B00000
418#define PLL_FBKDIV_12 0x00C00000
419#define PLL_FBKDIV_13 0x00D00000
420#define PLL_FBKDIV_14 0x00E00000
421#define PLL_FBKDIV_15 0x00F00000
422 /* Forward A divisor */
423#define PLL_FWDDIVA 0x00070000
424#define CPC0_PLLMR1_FWDVA 0x00070000
425#define PLL_FWDDIVA_8 0x00000000
426#define PLL_FWDDIVA_7 0x00010000
427#define PLL_FWDDIVA_6 0x00020000
428#define PLL_FWDDIVA_5 0x00030000
429#define PLL_FWDDIVA_4 0x00040000
430#define PLL_FWDDIVA_3 0x00050000
431#define PLL_FWDDIVA_2 0x00060000
432#define PLL_FWDDIVA_1 0x00070000
433 /* Forward B divisor */
434#define PLL_FWDDIVB 0x00007000
435#define CPC0_PLLMR1_FWDVB 0x00007000
436#define PLL_FWDDIVB_8 0x00000000
437#define PLL_FWDDIVB_7 0x00001000
438#define PLL_FWDDIVB_6 0x00002000
439#define PLL_FWDDIVB_5 0x00003000
440#define PLL_FWDDIVB_4 0x00004000
441#define PLL_FWDDIVB_3 0x00005000
442#define PLL_FWDDIVB_2 0x00006000
443#define PLL_FWDDIVB_1 0x00007000
444 /* PLL tune bits */
445#define PLL_TUNE_MASK 0x000003FF
446#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
447#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
448#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
449#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
450#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
451#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
452#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
453
454/* Defines for CPC0_PLLMR0 Register fields */
455 /* CPU divisor */
456#define PLL_CPUDIV 0x00300000
457#define CPC0_PLLMR0_CCDV 0x00300000
458#define PLL_CPUDIV_1 0x00000000
459#define PLL_CPUDIV_2 0x00100000
460#define PLL_CPUDIV_3 0x00200000
461#define PLL_CPUDIV_4 0x00300000
462 /* PLB divisor */
463#define PLL_PLBDIV 0x00030000
464#define CPC0_PLLMR0_CBDV 0x00030000
465#define PLL_PLBDIV_1 0x00000000
466#define PLL_PLBDIV_2 0x00010000
467#define PLL_PLBDIV_3 0x00020000
468#define PLL_PLBDIV_4 0x00030000
469 /* OPB divisor */
470#define PLL_OPBDIV 0x00003000
471#define CPC0_PLLMR0_OPDV 0x00003000
472#define PLL_OPBDIV_1 0x00000000
473#define PLL_OPBDIV_2 0x00001000
474#define PLL_OPBDIV_3 0x00002000
475#define PLL_OPBDIV_4 0x00003000
476 /* EBC divisor */
477#define PLL_EXTBUSDIV 0x00000300
478#define CPC0_PLLMR0_EPDV 0x00000300
479#define PLL_EXTBUSDIV_2 0x00000000
480#define PLL_EXTBUSDIV_3 0x00000100
481#define PLL_EXTBUSDIV_4 0x00000200
482#define PLL_EXTBUSDIV_5 0x00000300
483 /* MAL divisor */
484#define PLL_MALDIV 0x00000030
485#define CPC0_PLLMR0_MPDV 0x00000030
486#define PLL_MALDIV_1 0x00000000
487#define PLL_MALDIV_2 0x00000010
488#define PLL_MALDIV_3 0x00000020
489#define PLL_MALDIV_4 0x00000030
490 /* PCI divisor */
491#define PLL_PCIDIV 0x00000003
492#define CPC0_PLLMR0_PPFD 0x00000003
493#define PLL_PCIDIV_1 0x00000000
494#define PLL_PCIDIV_2 0x00000001
495#define PLL_PCIDIV_3 0x00000002
496#define PLL_PCIDIV_4 0x00000003
497
498/*
499 *-------------------------------------------------------------------------------
500 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
501 * assuming a 33.3MHz input clock to the 405EP.
502 *-------------------------------------------------------------------------------
503 */
504#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]505 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
506 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]507#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]508 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
509 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]510
511#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]512 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
513 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]514#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]515 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
516 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]517#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]518 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
519 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]520#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]521 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
522 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]523#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]524 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
525 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]526#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]527 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
528 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese317a25f2004-12-16 18:03:44 +0000[diff] [blame]529#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
wdenk07d7e6b2004-12-16 21:44:03 +0000[diff] [blame]530 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
531 PLL_MALDIV_1 | PLL_PCIDIV_2)
stroese317a25f2004-12-16 18:03:44 +0000[diff] [blame]532#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
wdenk07d7e6b2004-12-16 21:44:03 +0000[diff] [blame]533 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
534 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]535
536/*
537 * PLL Voltage Controlled Oscillator (VCO) definitions
538 * Maximum and minimum values (in MHz) for correct PLL operation.
539 */
540#define VCO_MIN 500
541#define VCO_MAX 1000
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]542#elif defined(CONFIG_405EZ)
543/******************************************************************************
544 * SDR Registers
545 ******************************************************************************/
546#define SDR_DCR_BASE 0x0E
547#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
548#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
549
Stefan Roese9d6eeef2007-05-22 12:48:09 +0200[diff] [blame^]550#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
551#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]552
553#define sdrnand0 0x4000
554#define sdrultra0 0x4040
555#define sdrultra1 0x4050
556#define sdricintstat 0x4510
557
558#define SDR_NAND0_NDEN 0x80000000
559
560#define SDR_ULTRA0_NDGPIOBP 0x80000000
561#define SDR_ULTRA0_CSN_MASK 0x78000000
562#define SDR_ULTRA0_CSNSEL0 0x40000000
563#define SDR_ULTRA0_CSNSEL1 0x20000000
564#define SDR_ULTRA0_CSNSEL2 0x10000000
565#define SDR_ULTRA0_CSNSEL3 0x08000000
566
567#define SDR_ULTRA1_LEDNENABLE 0x40000000
568
569#define SDR_ICRX_STAT 0x80000000
570#define SDR_ICTX0_STAT 0x40000000
571#define SDR_ICTX1_STAT 0x20000000
572
Stefan Roese3a75ac12007-04-18 12:05:59 +0200[diff] [blame]573#define SDR_PINSTP 0x40
574
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]575/******************************************************************************
576 * Control
577 ******************************************************************************/
578#define CNTRL_DCR_BASE 0x0C
579#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
580#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
581
582/* CPR Registers */
583#define cprclkupd 0x020 /* CPR_CLKUPD */
584#define cprpllc 0x040 /* CPR_PLLC */
585#define cprplld 0x060 /* CPR_PLLD */
586#define cprprimad 0x080 /* CPR_PRIMAD */
587#define cprperd0 0x0e0 /* CPR_PERD0 */
588#define cprperd1 0x0e1 /* CPR_PERD1 */
589#define cprperc0 0x180 /* CPR_PERC0 */
590#define cprmisc0 0x181 /* CPR_MISC0 */
591#define cprmisc1 0x182 /* CPR_MISC1 */
592
593/*
594 * Macro for accessing the indirect CPR register
595 */
Stefan Roese9d6eeef2007-05-22 12:48:09 +0200[diff] [blame^]596#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
597#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]598
599#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
600#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
601#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
602
603#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
604#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
605#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
606
607#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
608#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
609#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
610#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
611
612#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
613#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
614#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
615#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
616
617#if 0 /* Deprecated */
618#define CNTRL_DCR_BASE 0x0f0
619#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
620#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
621#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
622#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
623#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
624#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
625
626#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
627#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
628#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
629#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
630#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
631#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
632#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
633#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
634#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
635#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
636
637/* Bit definitions */
638#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
639#define PLLMR0_CPU_DIV_BYPASS 0x00000000
640#define PLLMR0_CPU_DIV_2 0x00100000
641#define PLLMR0_CPU_DIV_3 0x00200000
642#define PLLMR0_CPU_DIV_4 0x00300000
643
644#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
645#define PLLMR0_CPU_PLB_DIV_1 0x00000000
646#define PLLMR0_CPU_PLB_DIV_2 0x00010000
647#define PLLMR0_CPU_PLB_DIV_3 0x00020000
648#define PLLMR0_CPU_PLB_DIV_4 0x00030000
649
650#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
651#define PLLMR0_OPB_PLB_DIV_1 0x00000000
652#define PLLMR0_OPB_PLB_DIV_2 0x00001000
653#define PLLMR0_OPB_PLB_DIV_3 0x00002000
654#define PLLMR0_OPB_PLB_DIV_4 0x00003000
655
656#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
657#define PLLMR0_EXB_PLB_DIV_2 0x00000000
658#define PLLMR0_EXB_PLB_DIV_3 0x00000100
659#define PLLMR0_EXB_PLB_DIV_4 0x00000200
660#define PLLMR0_EXB_PLB_DIV_5 0x00000300
661
662#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
663#define PLLMR0_MAL_PLB_DIV_1 0x00000000
664#define PLLMR0_MAL_PLB_DIV_2 0x00000010
665#define PLLMR0_MAL_PLB_DIV_3 0x00000020
666#define PLLMR0_MAL_PLB_DIV_4 0x00000030
667
668#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
669#define PLLMR0_PCI_PLB_DIV_1 0x00000000
670#define PLLMR0_PCI_PLB_DIV_2 0x00000001
671#define PLLMR0_PCI_PLB_DIV_3 0x00000002
672#define PLLMR0_PCI_PLB_DIV_4 0x00000003
673
674#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
675#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
676#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
677#define PLLMR1_FBMUL_DIV_16 0x00000000
678#define PLLMR1_FBMUL_DIV_1 0x00100000
679#define PLLMR1_FBMUL_DIV_2 0x00200000
680#define PLLMR1_FBMUL_DIV_3 0x00300000
681#define PLLMR1_FBMUL_DIV_4 0x00400000
682#define PLLMR1_FBMUL_DIV_5 0x00500000
683#define PLLMR1_FBMUL_DIV_6 0x00600000
684#define PLLMR1_FBMUL_DIV_7 0x00700000
685#define PLLMR1_FBMUL_DIV_8 0x00800000
686#define PLLMR1_FBMUL_DIV_9 0x00900000
687#define PLLMR1_FBMUL_DIV_10 0x00A00000
688#define PLLMR1_FBMUL_DIV_11 0x00B00000
689#define PLLMR1_FBMUL_DIV_12 0x00C00000
690#define PLLMR1_FBMUL_DIV_13 0x00D00000
691#define PLLMR1_FBMUL_DIV_14 0x00E00000
692#define PLLMR1_FBMUL_DIV_15 0x00F00000
693
694#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
695#define PLLMR1_FWDVA_DIV_8 0x00000000
696#define PLLMR1_FWDVA_DIV_7 0x00010000
697#define PLLMR1_FWDVA_DIV_6 0x00020000
698#define PLLMR1_FWDVA_DIV_5 0x00030000
699#define PLLMR1_FWDVA_DIV_4 0x00040000
700#define PLLMR1_FWDVA_DIV_3 0x00050000
701#define PLLMR1_FWDVA_DIV_2 0x00060000
702#define PLLMR1_FWDVA_DIV_1 0x00070000
703#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
704#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
705
706/* Defines for CPC0_EPRCSR register */
707#define CPC0_EPRCSR_E0NFE 0x80000000
708#define CPC0_EPRCSR_E1NFE 0x40000000
709#define CPC0_EPRCSR_E1RPP 0x00000080
710#define CPC0_EPRCSR_E0RPP 0x00000040
711#define CPC0_EPRCSR_E1ERP 0x00000020
712#define CPC0_EPRCSR_E0ERP 0x00000010
713#define CPC0_EPRCSR_E1PCI 0x00000002
714#define CPC0_EPRCSR_E0PCI 0x00000001
715
716/* Defines for CPC0_BOOR Register */
717#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
718
719/* Defines for CPC0_PLLMR1 Register fields */
720#define PLL_ACTIVE 0x80000000
721#define CPC0_PLLMR1_SSCS 0x80000000
722#define PLL_RESET 0x40000000
723#define CPC0_PLLMR1_PLLR 0x40000000
724 /* Feedback multiplier */
725#define PLL_FBKDIV 0x00F00000
726#define CPC0_PLLMR1_FBDV 0x00F00000
727#define PLL_FBKDIV_16 0x00000000
728#define PLL_FBKDIV_1 0x00100000
729#define PLL_FBKDIV_2 0x00200000
730#define PLL_FBKDIV_3 0x00300000
731#define PLL_FBKDIV_4 0x00400000
732#define PLL_FBKDIV_5 0x00500000
733#define PLL_FBKDIV_6 0x00600000
734#define PLL_FBKDIV_7 0x00700000
735#define PLL_FBKDIV_8 0x00800000
736#define PLL_FBKDIV_9 0x00900000
737#define PLL_FBKDIV_10 0x00A00000
738#define PLL_FBKDIV_11 0x00B00000
739#define PLL_FBKDIV_12 0x00C00000
740#define PLL_FBKDIV_13 0x00D00000
741#define PLL_FBKDIV_14 0x00E00000
742#define PLL_FBKDIV_15 0x00F00000
743 /* Forward A divisor */
744#define PLL_FWDDIVA 0x00070000
745#define CPC0_PLLMR1_FWDVA 0x00070000
746#define PLL_FWDDIVA_8 0x00000000
747#define PLL_FWDDIVA_7 0x00010000
748#define PLL_FWDDIVA_6 0x00020000
749#define PLL_FWDDIVA_5 0x00030000
750#define PLL_FWDDIVA_4 0x00040000
751#define PLL_FWDDIVA_3 0x00050000
752#define PLL_FWDDIVA_2 0x00060000
753#define PLL_FWDDIVA_1 0x00070000
754 /* Forward B divisor */
755#define PLL_FWDDIVB 0x00007000
756#define CPC0_PLLMR1_FWDVB 0x00007000
757#define PLL_FWDDIVB_8 0x00000000
758#define PLL_FWDDIVB_7 0x00001000
759#define PLL_FWDDIVB_6 0x00002000
760#define PLL_FWDDIVB_5 0x00003000
761#define PLL_FWDDIVB_4 0x00004000
762#define PLL_FWDDIVB_3 0x00005000
763#define PLL_FWDDIVB_2 0x00006000
764#define PLL_FWDDIVB_1 0x00007000
765 /* PLL tune bits */
766#define PLL_TUNE_MASK 0x000003FF
767#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
768#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
769#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
770#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
771#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
772#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
773#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
774
775/* Defines for CPC0_PLLMR0 Register fields */
776 /* CPU divisor */
777#define PLL_CPUDIV 0x00300000
778#define CPC0_PLLMR0_CCDV 0x00300000
779#define PLL_CPUDIV_1 0x00000000
780#define PLL_CPUDIV_2 0x00100000
781#define PLL_CPUDIV_3 0x00200000
782#define PLL_CPUDIV_4 0x00300000
783 /* PLB divisor */
784#define PLL_PLBDIV 0x00030000
785#define CPC0_PLLMR0_CBDV 0x00030000
786#define PLL_PLBDIV_1 0x00000000
787#define PLL_PLBDIV_2 0x00010000
788#define PLL_PLBDIV_3 0x00020000
789#define PLL_PLBDIV_4 0x00030000
790 /* OPB divisor */
791#define PLL_OPBDIV 0x00003000
792#define CPC0_PLLMR0_OPDV 0x00003000
793#define PLL_OPBDIV_1 0x00000000
794#define PLL_OPBDIV_2 0x00001000
795#define PLL_OPBDIV_3 0x00002000
796#define PLL_OPBDIV_4 0x00003000
797 /* EBC divisor */
798#define PLL_EXTBUSDIV 0x00000300
799#define CPC0_PLLMR0_EPDV 0x00000300
800#define PLL_EXTBUSDIV_2 0x00000000
801#define PLL_EXTBUSDIV_3 0x00000100
802#define PLL_EXTBUSDIV_4 0x00000200
803#define PLL_EXTBUSDIV_5 0x00000300
804 /* MAL divisor */
805#define PLL_MALDIV 0x00000030
806#define CPC0_PLLMR0_MPDV 0x00000030
807#define PLL_MALDIV_1 0x00000000
808#define PLL_MALDIV_2 0x00000010
809#define PLL_MALDIV_3 0x00000020
810#define PLL_MALDIV_4 0x00000030
811 /* PCI divisor */
812#define PLL_PCIDIV 0x00000003
813#define CPC0_PLLMR0_PPFD 0x00000003
814#define PLL_PCIDIV_1 0x00000000
815#define PLL_PCIDIV_2 0x00000001
816#define PLL_PCIDIV_3 0x00000002
817#define PLL_PCIDIV_4 0x00000003
818
819/*
820 *-------------------------------------------------------------------------------
821 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
822 * assuming a 33.3MHz input clock to the 405EP.
823 *-------------------------------------------------------------------------------
824 */
825#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
826 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
827 PLL_MALDIV_1 | PLL_PCIDIV_4)
828#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
829 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
830 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
831#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
832 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
833 PLL_MALDIV_1 | PLL_PCIDIV_4)
834#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
835 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
836 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
837#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
838 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
839 PLL_MALDIV_1 | PLL_PCIDIV_4)
840#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
841 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
842 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
843#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
844 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
845 PLL_MALDIV_1 | PLL_PCIDIV_4)
846#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
847 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
848 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
849#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
850 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
851 PLL_MALDIV_1 | PLL_PCIDIV_2)
852#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
853 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
854 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
855
856/*
857 * PLL Voltage Controlled Oscillator (VCO) definitions
858 * Maximum and minimum values (in MHz) for correct PLL operation.
859 */
860#define VCO_MIN 500
861#define VCO_MAX 1000
862#endif /* #if 0 */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]863#else /* #ifdef CONFIG_405EP */
864/******************************************************************************
865 * Control
866 ******************************************************************************/
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]867#define CNTRL_DCR_BASE 0x0b0
868#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
869#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
870#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
871#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
872#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]873
874#define ecr (0xaa) /* edge conditioner register (405gpr) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]875
876/* Bit definitions */
877#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
878#define PLLMR_FWD_DIV_BYPASS 0xE0000000
879#define PLLMR_FWD_DIV_3 0xA0000000
880#define PLLMR_FWD_DIV_4 0x80000000
881#define PLLMR_FWD_DIV_6 0x40000000
882
883#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
884#define PLLMR_FB_DIV_1 0x02000000
885#define PLLMR_FB_DIV_2 0x04000000
886#define PLLMR_FB_DIV_3 0x06000000
887#define PLLMR_FB_DIV_4 0x08000000
888
889#define PLLMR_TUNING_MASK 0x01F80000
890
891#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
892#define PLLMR_CPU_PLB_DIV_1 0x00000000
893#define PLLMR_CPU_PLB_DIV_2 0x00020000
894#define PLLMR_CPU_PLB_DIV_3 0x00040000
895#define PLLMR_CPU_PLB_DIV_4 0x00060000
896
897#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
898#define PLLMR_OPB_PLB_DIV_1 0x00000000
899#define PLLMR_OPB_PLB_DIV_2 0x00008000
900#define PLLMR_OPB_PLB_DIV_3 0x00010000
901#define PLLMR_OPB_PLB_DIV_4 0x00018000
902
903#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
904#define PLLMR_PCI_PLB_DIV_1 0x00000000
905#define PLLMR_PCI_PLB_DIV_2 0x00002000
906#define PLLMR_PCI_PLB_DIV_3 0x00004000
907#define PLLMR_PCI_PLB_DIV_4 0x00006000
908
909#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
910#define PLLMR_EXB_PLB_DIV_2 0x00000000
911#define PLLMR_EXB_PLB_DIV_3 0x00000800
912#define PLLMR_EXB_PLB_DIV_4 0x00001000
913#define PLLMR_EXB_PLB_DIV_5 0x00001800
914
915/* definitions for PPC405GPr (new mode strapping) */
916#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
917
918#define PSR_PLL_FWD_MASK 0xC0000000
919#define PSR_PLL_FDBACK_MASK 0x30000000
920#define PSR_PLL_TUNING_MASK 0x0E000000
921#define PSR_PLB_CPU_MASK 0x01800000
922#define PSR_OPB_PLB_MASK 0x00600000
923#define PSR_PCI_PLB_MASK 0x00180000
924#define PSR_EB_PLB_MASK 0x00060000
925#define PSR_ROM_WIDTH_MASK 0x00018000
926#define PSR_ROM_LOC 0x00004000
927#define PSR_PCI_ASYNC_EN 0x00001000
928#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
929#define PSR_PCI_ARBIT_EN 0x00000400
930#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
931
stroese317a25f2004-12-16 18:03:44 +0000[diff] [blame]932#ifndef CONFIG_IOP480
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]933/*
934 * PLL Voltage Controlled Oscillator (VCO) definitions
935 * Maximum and minimum values (in MHz) for correct PLL operation.
936 */
937#define VCO_MIN 400
938#define VCO_MAX 800
stroese317a25f2004-12-16 18:03:44 +0000[diff] [blame]939#endif /* #ifndef CONFIG_IOP480 */
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]940#endif /* #ifdef CONFIG_405EP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]941
942/******************************************************************************
943 * Memory Access Layer
944 ******************************************************************************/
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]945#if defined(CONFIG_405EZ)
946#define MAL_DCR_BASE 0x380
947#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
948#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
949#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
950#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
951#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
952#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
953#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
954#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
955/* 0x08-0x0F Reserved */
956#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
957#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
958#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
959#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
960/* 0x14-0x1F Reserved */
961#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
962#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
963#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
964#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
965#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
966#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
967#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
968#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
969#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
970#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
971#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
972#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
973#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
974#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
975#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
976#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
977#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
978#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
979#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
980#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
981#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
982#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
983#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
984#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
985#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
986#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
987#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
988#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
989#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
990#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
991#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
992#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
993#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
994#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
995#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
996#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
997#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
998#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
999#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
1000#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
1001#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
1002#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
1003#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
1004#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
1005#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
1006#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
1007#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
1008#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
1009#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
1010#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
1011#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
1012#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
1013#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
1014#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
1015#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
1016#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
1017#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
1018#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
1019#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
1020#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
1021#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
1022#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
1023#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
1024#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
1025#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1026#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1027#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1028#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
1029#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
1030#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
1031#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
1032#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
1033#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
1034#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
1035#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
1036#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
1037#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
1038#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
1039#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
1040#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
1041#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
1042#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
1043#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
1044#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
1045#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
1046#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
1047#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
1048#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
1049#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
1050#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
1051#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
1052#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
1053#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
1054#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
1055#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
1056#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
1057
1058#else /* !defined(CONFIG_405EZ) */
1059
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1060#define MAL_DCR_BASE 0x180
1061#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1062#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1063#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1064#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1065#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
1066#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1067#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
1068#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1069#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
1070#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1071#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
1072#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1073#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1074#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenk2a6109c2004-06-06 23:53:59 +0000[diff] [blame]1075#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1076#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
wdenk2a6109c2004-06-06 23:53:59 +0000[diff] [blame]1077#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1078#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
wdenk2a6109c2004-06-06 23:53:59 +0000[diff] [blame]1079#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]1080#endif /* defined(CONFIG_405EZ) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1081
1082/*-----------------------------------------------------------------------------
1083| IIC Register Offsets
1084'----------------------------------------------------------------------------*/
1085#define IICMDBUF 0x00
1086#define IICSDBUF 0x02
1087#define IICLMADR 0x04
1088#define IICHMADR 0x05
1089#define IICCNTL 0x06
1090#define IICMDCNTL 0x07
1091#define IICSTS 0x08
1092#define IICEXTSTS 0x09
1093#define IICLSADR 0x0A
1094#define IICHSADR 0x0B
1095#define IICCLKDIV 0x0C
1096#define IICINTRMSK 0x0D
1097#define IICXFRCNT 0x0E
1098#define IICXTCNTLSS 0x0F
1099#define IICDIRECTCNTL 0x10
1100
1101/*-----------------------------------------------------------------------------
1102| UART Register Offsets
1103'----------------------------------------------------------------------------*/
1104#define DATA_REG 0x00
1105#define DL_LSB 0x00
1106#define DL_MSB 0x01
1107#define INT_ENABLE 0x01
1108#define FIFO_CONTROL 0x02
1109#define LINE_CONTROL 0x03
1110#define MODEM_CONTROL 0x04
1111#define LINE_STATUS 0x05
1112#define MODEM_STATUS 0x06
1113#define SCRATCH 0x07
1114
1115/******************************************************************************
1116 * On Chip Memory
1117 ******************************************************************************/
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]1118#if defined(CONFIG_405EZ)
1119#define OCM_DCR_BASE 0x020
1120#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
1121#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
1122#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
1123#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
1124#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
1125#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
1126#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
1127#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
1128#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
1129#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
1130#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
1131#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
1132#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
1133#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
1134#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
1135#else
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1136#define OCM_DCR_BASE 0x018
1137#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
1138#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
1139#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
1140#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]1141#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1142
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]1143/******************************************************************************
1144 * GPIO macro register defines
1145 ******************************************************************************/
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]1146#if defined(CONFIG_405EZ)
1147/* Only the 405EZ has 2 GPIOs */
1148#define GPIO_BASE 0xEF600700
1149#define GPIO0_OR (GPIO_BASE+0x0)
1150#define GPIO0_TCR (GPIO_BASE+0x4)
1151#define GPIO0_OSRL (GPIO_BASE+0x8)
1152#define GPIO0_OSRH (GPIO_BASE+0xC)
1153#define GPIO0_TSRL (GPIO_BASE+0x10)
1154#define GPIO0_TSRH (GPIO_BASE+0x14)
1155#define GPIO0_ODR (GPIO_BASE+0x18)
1156#define GPIO0_IR (GPIO_BASE+0x1C)
1157#define GPIO0_RR1 (GPIO_BASE+0x20)
1158#define GPIO0_RR2 (GPIO_BASE+0x24)
1159#define GPIO0_RR3 (GPIO_BASE+0x28)
1160#define GPIO0_ISR1L (GPIO_BASE+0x30)
1161#define GPIO0_ISR1H (GPIO_BASE+0x34)
1162#define GPIO0_ISR2L (GPIO_BASE+0x38)
1163#define GPIO0_ISR2H (GPIO_BASE+0x3C)
1164#define GPIO0_ISR3L (GPIO_BASE+0x40)
1165#define GPIO0_ISR3H (GPIO_BASE+0x44)
1166
1167#define GPIO1_BASE 0xEF600800
1168#define GPIO1_OR (GPIO1_BASE+0x0)
1169#define GPIO1_TCR (GPIO1_BASE+0x4)
1170#define GPIO1_OSRL (GPIO1_BASE+0x8)
1171#define GPIO1_OSRH (GPIO1_BASE+0xC)
1172#define GPIO1_TSRL (GPIO1_BASE+0x10)
1173#define GPIO1_TSRH (GPIO1_BASE+0x14)
1174#define GPIO1_ODR (GPIO1_BASE+0x18)
1175#define GPIO1_IR (GPIO1_BASE+0x1C)
1176#define GPIO1_RR1 (GPIO1_BASE+0x20)
1177#define GPIO1_RR2 (GPIO1_BASE+0x24)
1178#define GPIO1_RR3 (GPIO1_BASE+0x28)
1179#define GPIO1_ISR1L (GPIO1_BASE+0x30)
1180#define GPIO1_ISR1H (GPIO1_BASE+0x34)
1181#define GPIO1_ISR2L (GPIO1_BASE+0x38)
1182#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
1183#define GPIO1_ISR3L (GPIO1_BASE+0x40)
1184#define GPIO1_ISR3H (GPIO1_BASE+0x44)
1185
1186#else /* !405EZ */
1187
stroese434979e2003-05-23 11:18:02 +0000[diff] [blame]1188#define GPIO_BASE 0xEF600700
1189#define GPIO0_OR (GPIO_BASE+0x0)
1190#define GPIO0_TCR (GPIO_BASE+0x4)
1191#define GPIO0_OSRH (GPIO_BASE+0x8)
1192#define GPIO0_OSRL (GPIO_BASE+0xC)
1193#define GPIO0_TSRH (GPIO_BASE+0x10)
1194#define GPIO0_TSRL (GPIO_BASE+0x14)
1195#define GPIO0_ODR (GPIO_BASE+0x18)
1196#define GPIO0_IR (GPIO_BASE+0x1C)
1197#define GPIO0_RR1 (GPIO_BASE+0x20)
1198#define GPIO0_RR2 (GPIO_BASE+0x24)
1199#define GPIO0_ISR1H (GPIO_BASE+0x30)
1200#define GPIO0_ISR1L (GPIO_BASE+0x34)
1201#define GPIO0_ISR2H (GPIO_BASE+0x38)
1202#define GPIO0_ISR2L (GPIO_BASE+0x3C)
1203
Stefan Roese17ffbc82007-03-21 13:38:59 +0100[diff] [blame]1204#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1205
1206/*
1207 * Macro for accessing the indirect EBC register
1208 */
1209#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
1210#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
1211
1212
1213#ifndef __ASSEMBLY__
1214
1215typedef struct
1216{
1217 unsigned long pllFwdDiv;
1218 unsigned long pllFwdDivB;
1219 unsigned long pllFbkDiv;
1220 unsigned long pllPlbDiv;
1221 unsigned long pllPciDiv;
1222 unsigned long pllExtBusDiv;
1223 unsigned long pllOpbDiv;
1224 unsigned long freqVCOMhz; /* in MHz */
1225 unsigned long freqProcessor;
1226 unsigned long freqPLB;
1227 unsigned long freqPCI;
1228 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
1229 unsigned long pciClkSync; /* PCI clock is synchronous */
stroese317a25f2004-12-16 18:03:44 +0000[diff] [blame]1230 unsigned long freqVCOHz;
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1231} PPC405_SYS_INFO;
1232
1233#endif /* _ASMLANGUAGE */
1234
1235#define RESET_VECTOR 0xfffffffc
1236#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
1237 line aligned data. */
1238
1239#endif /* __PPC405_H__ */