blob: b1c28c9442dff555aa228beccb4d999594ae8a57 [file] [log] [blame]
Albert ARIBAUD6277b192013-02-25 00:58:58 +00001/*
2 * (C) Copyright 2002
3 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Albert ARIBAUD6277b192013-02-25 00:58:58 +000010 */
11
12MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
13 LENGTH = CONFIG_SPL_MAX_SIZE }
14MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
15 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
16
17OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
18OUTPUT_ARCH(arm)
19ENTRY(_start)
20SECTIONS
21{
22 .text :
23 {
24 __start = .;
25 arch/arm/cpu/armv7/start.o (.text)
26 *(.text*)
27 } >.sram
28
29 . = ALIGN(4);
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
31
32 . = ALIGN(4);
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
34
35 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +000036 KEEP(*(SORT(.u_boot_list*)));
Albert ARIBAUD6277b192013-02-25 00:58:58 +000037 } >.sram
38
39 . = ALIGN(4);
40 __image_copy_end = .;
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010041
42 .end :
43 {
44 *(.__end)
45 } >.sram
Albert ARIBAUD6277b192013-02-25 00:58:58 +000046
47 .bss :
48 {
49 . = ALIGN(4);
50 __bss_start = .;
51 *(.bss*)
52 . = ALIGN(4);
Tom Rini19aac972013-03-18 12:31:00 -040053 __bss_end = .;
Albert ARIBAUD6277b192013-02-25 00:58:58 +000054 } >.sdram
55}