| developer | d48dd9a | 2018-12-20 16:12:51 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_MTK_RESET_H_ |
| 7 | #define _DT_BINDINGS_MTK_RESET_H_ |
| 8 | |
| 9 | /* ETHSYS */ |
| 10 | #define ETHSYS_PPE_RST 31 |
| 11 | #define ETHSYS_EPHY_RST 24 |
| 12 | #define ETHSYS_GMAC_RST 23 |
| 13 | #define ETHSYS_ESW_RST 16 |
| 14 | #define ETHSYS_FE_RST 6 |
| 15 | #define ETHSYS_MCM_RST 2 |
| 16 | #define ETHSYS_SYS_RST 0 |
| 17 | |
| developer | a3d81fe | 2019-07-29 22:17:47 +0800 | [diff] [blame] | 18 | /* HIFSYS resets */ |
| 19 | #define HIFSYS_PCIE2_RST 26 |
| 20 | #define HIFSYS_PCIE1_RST 25 |
| 21 | #define HIFSYS_PCIE0_RST 24 |
| 22 | #define HIFSYS_UPHY1_RST 22 |
| 23 | #define HIFSYS_UPHY0_RST 21 |
| 24 | #define HIFSYS_UHOST1_RST 4 |
| 25 | #define HIFSYS_UHOST0_RST 3 |
| 26 | |
| developer | d48dd9a | 2018-12-20 16:12:51 +0800 | [diff] [blame] | 27 | #endif /* _DT_BINDINGS_MTK_RESET_H_ */ |