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git01.mediatek.com / filogic / uboot / 9c8af15f86b602d32dc0a1e638467c05b8792439 / . / src / arm / nxp / imx / imx6qdl-sabreauto.dtsi
blob: 35b6bec7a3fab62f4fd18dba267e5e5c1834284a [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8
9/ {
10 chosen {
11 stdout-path = &uart4;
12 };
13
14 memory@10000000 {
15 device_type = "memory";
16 reg = <0x10000000 0x80000000>;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_leds>;
23
24 led-user {
25 label = "debug";
26 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
27 };
28 };
29
30 gpio-keys {
31 compatible = "gpio-keys";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_gpio_keys>;
34
35 home {
36 label = "Home";
37 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
38 linux,code = <KEY_HOME>;
39 wakeup-source;
40 };
41
42 back {
43 label = "Back";
44 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
45 linux,code = <KEY_BACK>;
46 wakeup-source;
47 };
48
49 program {
50 label = "Program";
51 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
52 linux,code = <KEY_PROGRAM>;
53 wakeup-source;
54 };
55
56 volume-up {
57 label = "Volume Up";
58 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_VOLUMEUP>;
60 wakeup-source;
61 };
62
63 volume-down {
64 label = "Volume Down";
65 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
66 linux,code = <KEY_VOLUMEDOWN>;
67 wakeup-source;
68 };
69 };
70
71 clocks {
72 codec_osc: anaclk2 {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <24576000>;
76 };
77 };
78
79 reg_audio: regulator-audio {
80 compatible = "regulator-fixed";
81 regulator-name = "cs42888_supply";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86
87 reg_usb_h1_vbus: regulator-usb-h1-vbus {
88 compatible = "regulator-fixed";
89 regulator-name = "usb_h1_vbus";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
93 enable-active-high;
94 };
95
96 reg_usb_otg_vbus: regulator-usb-otg-vbus {
97 compatible = "regulator-fixed";
98 regulator-name = "usb_otg_vbus";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 };
104
105 reg_can_en: regulator-can-en {
106 compatible = "regulator-fixed";
107 regulator-name = "can-en";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
111 enable-active-high;
112 };
113
114 reg_can_stby: regulator-can-stby {
115 compatible = "regulator-fixed";
116 regulator-name = "can-stby";
117 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <3300000>;
119 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
120 enable-active-high;
121 vin-supply = <&reg_can_en>;
122 };
123
124 sound-cs42888 {
125 compatible = "fsl,imx6-sabreauto-cs42888",
126 "fsl,imx-audio-cs42888";
127 model = "imx-cs42888";
128 audio-cpu = <&esai>;
129 audio-asrc = <&asrc>;
130 audio-codec = <&codec>;
131 audio-routing =
132 "Line Out Jack", "AOUT1L",
133 "Line Out Jack", "AOUT1R",
134 "Line Out Jack", "AOUT2L",
135 "Line Out Jack", "AOUT2R",
136 "Line Out Jack", "AOUT3L",
137 "Line Out Jack", "AOUT3R",
138 "Line Out Jack", "AOUT4L",
139 "Line Out Jack", "AOUT4R",
140 "AIN1L", "Line In Jack",
141 "AIN1R", "Line In Jack",
142 "AIN2L", "Line In Jack",
143 "AIN2R", "Line In Jack";
144 };
145
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]146 spdif_in: spdif-in {
147 compatible = "linux,spdif-dir";
148 #sound-dai-cells = <0>;
149 };
150
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]151 sound-spdif {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]152 compatible = "fsl,imx-sabreauto-spdif",
153 "fsl,imx-audio-spdif";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]154 model = "imx-spdif";
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]155 audio-cpu = <&spdif>;
156 audio-codec = <&spdif_in>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]157 };
158
159 backlight {
160 compatible = "pwm-backlight";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]161 pwms = <&pwm3 0 5000000 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]162 brightness-levels = <0 4 8 16 32 64 128 255>;
163 default-brightness-level = <7>;
164 status = "okay";
165 };
166
167 i2cmux {
168 compatible = "i2c-mux-gpio";
169 #address-cells = <1>;
170 #size-cells = <0>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_i2c3mux>;
173 mux-gpios = <&gpio5 4 0>;
174 i2c-parent = <&i2c3>;
175 idle-state = <0>;
176
177 i2c@1 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 reg = <1>;
181
182 adv7180: camera@21 {
183 compatible = "adi,adv7180";
184 reg = <0x21>;
185 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
186 interrupt-parent = <&gpio1>;
187 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
188
189 port {
190 adv7180_to_ipu1_csi0_mux: endpoint {
191 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
192 bus-width = <8>;
193 };
194 };
195 };
196
197 max7310_a: gpio@30 {
198 compatible = "maxim,max7310";
199 reg = <0x30>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 };
203
204 max7310_b: gpio@32 {
205 compatible = "maxim,max7310";
206 reg = <0x32>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_max7310>;
211 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
212 };
213
214 max7310_c: gpio@34 {
215 compatible = "maxim,max7310";
216 reg = <0x34>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 };
220
221 light-sensor@44 {
222 compatible = "isil,isl29023";
223 reg = <0x44>;
224 interrupt-parent = <&gpio5>;
225 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
226 };
227
228 magnetometer@e {
229 compatible = "fsl,mag3110";
230 reg = <0x0e>;
231 interrupt-parent = <&gpio2>;
232 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
233 };
234
235 accelerometer@1c {
236 compatible = "fsl,mma8451";
237 reg = <0x1c>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_mma8451_int>;
240 interrupt-parent = <&gpio6>;
241 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
242 };
243 };
244 };
245};
246
247&ipu1_csi0_from_ipu1_csi0_mux {
248 bus-width = <8>;
249};
250
251&ipu1_csi0_mux_from_parallel_sensor {
252 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
253 bus-width = <8>;
254};
255
256&ipu1_csi0 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_ipu1_csi0>;
259};
260
261&clks {
262 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
263 <&clks IMX6QDL_PLL4_BYPASS>,
264 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
265 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
266 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
267 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
268 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
269 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
270 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
271 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
272};
273
274&ecspi1 {
275 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
278 status = "disabled"; /* pin conflict with WEIM NOR */
279
280 flash: flash@0 {
281 #address-cells = <1>;
282 #size-cells = <1>;
283 compatible = "st,m25p32", "jedec,spi-nor";
284 spi-max-frequency = <20000000>;
285 reg = <0>;
286 };
287};
288
289&esai {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_esai>;
292 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
293 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
294 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
295 assigned-clock-rates = <0>, <24576000>;
296 status = "okay";
297};
298
299&fec {
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_enet>;
302 phy-mode = "rgmii-id";
303 /delete-property/ interrupts;
304 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
305 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
306 fsl,err006687-workaround-present;
307 fsl,magic-packet;
308 status = "okay";
309};
310
311&can1 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_flexcan1>;
314 xceiver-supply = <&reg_can_stby>;
315 status = "disabled"; /* pin conflict with fec */
316};
317
318&can2 {
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_flexcan2>;
321 xceiver-supply = <&reg_can_stby>;
322 status = "okay";
323};
324
325&gpmi {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_gpmi_nand>;
328 status = "okay";
329};
330
331&hdmi {
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_hdmi_cec>;
334 ddc-i2c-bus = <&i2c2>;
335 status = "okay";
336};
337
338&i2c2 {
339 clock-frequency = <100000>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_i2c2>;
342 status = "okay";
343
344 pmic: pmic@8 {
345 compatible = "fsl,pfuze100";
346 reg = <0x08>;
347
348 regulators {
349 sw1a_reg: sw1ab {
350 regulator-min-microvolt = <300000>;
351 regulator-max-microvolt = <1875000>;
352 regulator-boot-on;
353 regulator-always-on;
354 regulator-ramp-delay = <6250>;
355 };
356
357 sw1c_reg: sw1c {
358 regulator-min-microvolt = <300000>;
359 regulator-max-microvolt = <1875000>;
360 regulator-boot-on;
361 regulator-always-on;
362 regulator-ramp-delay = <6250>;
363 };
364
365 sw2_reg: sw2 {
366 regulator-min-microvolt = <800000>;
367 regulator-max-microvolt = <3300000>;
368 regulator-boot-on;
369 regulator-always-on;
370 };
371
372 sw3a_reg: sw3a {
373 regulator-min-microvolt = <400000>;
374 regulator-max-microvolt = <1975000>;
375 regulator-boot-on;
376 regulator-always-on;
377 };
378
379 sw3b_reg: sw3b {
380 regulator-min-microvolt = <400000>;
381 regulator-max-microvolt = <1975000>;
382 regulator-boot-on;
383 regulator-always-on;
384 };
385
386 sw4_reg: sw4 {
387 regulator-min-microvolt = <800000>;
388 regulator-max-microvolt = <3300000>;
389 };
390
391 swbst_reg: swbst {
392 regulator-min-microvolt = <5000000>;
393 regulator-max-microvolt = <5150000>;
394 };
395
396 snvs_reg: vsnvs {
397 regulator-min-microvolt = <1000000>;
398 regulator-max-microvolt = <3000000>;
399 regulator-boot-on;
400 regulator-always-on;
401 };
402
403 vref_reg: vrefddr {
404 regulator-boot-on;
405 regulator-always-on;
406 };
407
408 vgen1_reg: vgen1 {
409 regulator-min-microvolt = <800000>;
410 regulator-max-microvolt = <1550000>;
411 };
412
413 vgen2_reg: vgen2 {
414 regulator-min-microvolt = <800000>;
415 regulator-max-microvolt = <1550000>;
416 };
417
418 vgen3_reg: vgen3 {
419 regulator-min-microvolt = <1800000>;
420 regulator-max-microvolt = <3300000>;
421 };
422
423 vgen4_reg: vgen4 {
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-always-on;
427 };
428
429 vgen5_reg: vgen5 {
430 regulator-min-microvolt = <1800000>;
431 regulator-max-microvolt = <3300000>;
432 regulator-always-on;
433 };
434
435 vgen6_reg: vgen6 {
436 regulator-min-microvolt = <1800000>;
437 regulator-max-microvolt = <3300000>;
438 regulator-always-on;
439 };
440 };
441 };
442
443 codec: cs42888@48 {
444 compatible = "cirrus,cs42888";
445 reg = <0x48>;
446 clocks = <&codec_osc>;
447 clock-names = "mclk";
448 VA-supply = <&reg_audio>;
449 VD-supply = <&reg_audio>;
450 VLS-supply = <&reg_audio>;
451 VLC-supply = <&reg_audio>;
452 };
453
454 touchscreen@4 {
455 compatible = "eeti,egalax_ts";
456 reg = <0x04>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_egalax_int>;
459 interrupt-parent = <&gpio2>;
460 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
461 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
462 };
463};
464
465&i2c3 {
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_i2c3>;
468 status = "okay";
469};
470
471&iomuxc {
472 pinctrl-names = "default";
473 pinctrl-0 = <&pinctrl_hog>;
474
475 imx6qdl-sabreauto {
476 pinctrl_hog: hoggrp {
477 fsl,pins = <
478 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
479 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
480 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
481 >;
482 };
483
484 pinctrl_ecspi1: ecspi1grp {
485 fsl,pins = <
486 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
487 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
488 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
489 >;
490 };
491
492 pinctrl_ecspi1_cs: ecspi1cs {
493 fsl,pins = <
494 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
495 >;
496 };
497
498 pinctrl_egalax_int: egalax-intgrp {
499 fsl,pins = <
500 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
501 >;
502 };
503
504 pinctrl_enet: enetgrp {
505 fsl,pins = <
506 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
507 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
508 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
509 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
510 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
511 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
512 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
513 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
514 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
515 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
516 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
517 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
518 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
519 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
520 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
521 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
522 >;
523 };
524
525 pinctrl_esai: esaigrp {
526 fsl,pins = <
527 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
528 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
529 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
530 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
531 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
532 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
533 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
534 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
535 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
536 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
537 >;
538 };
539
540 pinctrl_flexcan1: flexcan1grp {
541 fsl,pins = <
542 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
543 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
544 >;
545 };
546
547 pinctrl_flexcan2: flexcan2grp {
548 fsl,pins = <
549 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
550 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
551 >;
552 };
553
554 pinctrl_gpio_keys: gpiokeysgrp {
555 fsl,pins = <
556 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
557 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
558 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
559 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
560 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
561 >;
562 };
563
564 pinctrl_gpio_leds: gpioledsgrp {
565 fsl,pins = <
566 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
567 >;
568 };
569
570 pinctrl_gpmi_nand: gpminandgrp {
571 fsl,pins = <
572 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
573 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
574 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
575 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
576 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
577 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
578 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
579 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
580 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
581 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
582 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
583 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
584 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
585 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
586 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
587 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
588 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
589 >;
590 };
591
592 pinctrl_hdmi_cec: hdmicecgrp {
593 fsl,pins = <
594 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
595 >;
596 };
597
598 pinctrl_i2c2: i2c2grp {
599 fsl,pins = <
600 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
601 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
602 >;
603 };
604
605 pinctrl_i2c3: i2c3grp {
606 fsl,pins = <
607 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
608 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
609 >;
610 };
611
612 pinctrl_i2c3mux: i2c3muxgrp {
613 fsl,pins = <
614 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
615 >;
616 };
617
618 pinctrl_ipu1_csi0: ipu1csi0grp {
619 fsl,pins = <
620 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
621 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
622 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
623 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
624 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
625 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
626 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
627 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
628 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
629 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
630 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
631 >;
632 };
633
634 pinctrl_max7310: max7310grp {
635 fsl,pins = <
636 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
637 >;
638 };
639
640 pinctrl_mma8451_int: mma8451intgrp {
641 fsl,pins = <
642 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1
643 >;
644 };
645
646 pinctrl_pwm3: pwm1grp {
647 fsl,pins = <
648 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
649 >;
650 };
651
652 pinctrl_gpt_input_capture0: gptinputcapture0grp {
653 fsl,pins = <
654 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
655 >;
656 };
657
658 pinctrl_gpt_input_capture1: gptinputcapture1grp {
659 fsl,pins = <
660 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
661 >;
662 };
663
664 pinctrl_spdif: spdifgrp {
665 fsl,pins = <
666 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
667 >;
668 };
669
670 pinctrl_uart4: uart4grp {
671 fsl,pins = <
672 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
673 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
674 >;
675 };
676
677 pinctrl_usbotg: usbotggrp {
678 fsl,pins = <
679 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
680 >;
681 };
682
683 pinctrl_usdhc3: usdhc3grp {
684 fsl,pins = <
685 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
686 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
687 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
688 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
689 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
690 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
691 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
692 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
693 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
694 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
695 >;
696 };
697
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]698 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]699 fsl,pins = <
700 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
701 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
702 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
703 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
704 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
705 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
706 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
707 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
708 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
709 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
710 >;
711 };
712
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]713 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]714 fsl,pins = <
715 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
716 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
717 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
718 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
719 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
720 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
721 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
722 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
723 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
724 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
725 >;
726 };
727
728 pinctrl_weim_cs0: weimcs0grp {
729 fsl,pins = <
730 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
731 >;
732 };
733
734 pinctrl_weim_nor: weimnorgrp {
735 fsl,pins = <
736 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
737 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
738 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
739 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
740 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
741 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
742 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
743 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
744 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
745 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
746 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
747 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
748 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
749 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
750 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
751 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
752 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
753 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
754 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
755 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
756 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
757 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
758 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
759 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
760 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
761 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
762 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
763 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
764 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
765 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
766 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
767 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
768 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
769 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
770 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
771 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
772 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
773 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
774 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
775 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
776 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
777 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
778 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
779 >;
780 };
781 };
782};
783
784&ldb {
785 status = "okay";
786
787 lvds-channel@0 {
788 fsl,data-mapping = "spwg";
789 fsl,data-width = <18>;
790 status = "okay";
791
792 display-timings {
793 native-mode = <&timing0>;
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]794 timing0: timing-hsd100pxn1 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]795 clock-frequency = <65000000>;
796 hactive = <1024>;
797 vactive = <768>;
798 hback-porch = <220>;
799 hfront-porch = <40>;
800 vback-porch = <21>;
801 vfront-porch = <7>;
802 hsync-len = <60>;
803 vsync-len = <10>;
804 };
805 };
806 };
807};
808
809&pwm3 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_pwm3>;
812 status = "okay";
813};
814
815&pcie {
816 status = "okay";
817};
818
819&spdif {
820 pinctrl-names = "default";
821 pinctrl-0 = <&pinctrl_spdif>;
822 status = "okay";
823};
824
825&uart4 {
826 pinctrl-names = "default";
827 pinctrl-0 = <&pinctrl_uart4>;
828 status = "okay";
829};
830
831&usbh1 {
832 vbus-supply = <&reg_usb_h1_vbus>;
833 status = "okay";
834};
835
836&usbotg {
837 vbus-supply = <&reg_usb_otg_vbus>;
838 pinctrl-names = "default";
839 pinctrl-0 = <&pinctrl_usbotg>;
840 status = "okay";
841};
842
843&usdhc3 {
844 pinctrl-names = "default", "state_100mhz", "state_200mhz";
845 pinctrl-0 = <&pinctrl_usdhc3>;
846 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
847 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
848 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
849 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
850 status = "okay";
851};
852
853&weim {
854 pinctrl-names = "default";
855 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
856 ranges = <0 0 0x08000000 0x08000000>;
857 status = "disabled"; /* pin conflict with SPI NOR */
858
859 nor@0,0 {
860 compatible = "cfi-flash";
861 reg = <0 0 0x02000000>;
862 #address-cells = <1>;
863 #size-cells = <1>;
864 bank-width = <2>;
865 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
866 0x0000c000 0x1404a38e 0x00000000>;
867 };
868};