Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Mediatek MT7530 and MT7531 Ethernet Switches |
| 8 | |
| 9 | maintainers: |
| 10 | - Arınç ÜNAL <arinc.unal@arinc9.com> |
| 11 | - Landen Chao <Landen.Chao@mediatek.com> |
| 12 | - DENG Qingfang <dqfext@gmail.com> |
| 13 | - Sean Wang <sean.wang@mediatek.com> |
| 14 | - Daniel Golle <daniel@makrotopia.org> |
| 15 | |
| 16 | description: | |
| 17 | There are three versions of MT7530, standalone, in a multi-chip module and |
| 18 | built-into a SoC. |
| 19 | |
| 20 | MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, |
| 21 | MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. |
| 22 | |
| 23 | The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four |
| 24 | Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's |
Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 25 | memory map rather than using MDIO. The switch has an internally connected 10G |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 26 | CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. |
| 27 | |
Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 28 | The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 29 | and the switch registers are directly mapped into SoC's memory map rather than |
| 30 | using MDIO. The DSA driver currently doesn't support MT7620 variants. |
| 31 | |
| 32 | There is only the standalone version of MT7531. |
| 33 | |
Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 34 | Port 5 on MT7530 supports various configurations: |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 35 | |
| 36 | - Port 5 can be used as a CPU port. |
| 37 | |
| 38 | - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, |
| 39 | the gmac of the SoC which is wired to port 5 can connect to the PHY. |
| 40 | This is usually used for connecting the wan port directly to the CPU to |
| 41 | achieve 2 Gbps routing in total. |
| 42 | |
| 43 | The driver looks up the reg on the ethernet-phy node, which the phy-handle |
| 44 | property on the gmac node refers to, to mux the specified phy. |
| 45 | |
| 46 | The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the |
| 47 | compatible string and the reg must be 1. So, for now, only gmac1 of a |
| 48 | MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. |
| 49 | |
| 50 | For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. |
| 51 | |
| 52 | Check out example 5. |
| 53 | |
| 54 | - For the multi-chip module MT7530, in case of an external phy wired to |
| 55 | gmac1 of the SoC, port 5 must not be enabled. |
| 56 | |
| 57 | In case of muxing PHY 0 or 4, the external phy must not be enabled. |
| 58 | |
| 59 | For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. |
| 60 | |
| 61 | Check out example 6. |
| 62 | |
| 63 | - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port. |
| 64 | |
| 65 | For the multi-chip module MT7530, the external phy must be wired TX to TX |
| 66 | to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired |
| 67 | this way. |
| 68 | |
| 69 | For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the |
| 70 | external phy is connected TX to TX. |
| 71 | |
| 72 | For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. |
| 73 | |
| 74 | Check out example 7. |
| 75 | |
| 76 | properties: |
| 77 | compatible: |
| 78 | oneOf: |
| 79 | - description: |
| 80 | Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC |
| 81 | const: mediatek,mt7530 |
| 82 | |
| 83 | - description: |
| 84 | Standalone MT7531 |
| 85 | const: mediatek,mt7531 |
| 86 | |
| 87 | - description: |
| 88 | Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs |
| 89 | const: mediatek,mt7621 |
| 90 | |
| 91 | - description: |
| 92 | Built-in switch of the MT7988 SoC |
| 93 | const: mediatek,mt7988-switch |
| 94 | |
Tom Rini | 9c8af15 | 2024-12-24 12:03:04 -0600 | [diff] [blame^] | 95 | - description: |
| 96 | Built-in switch of the Airoha EN7581 SoC |
| 97 | const: airoha,en7581-switch |
| 98 | |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 99 | reg: |
| 100 | maxItems: 1 |
| 101 | |
| 102 | core-supply: |
| 103 | description: |
| 104 | Phandle to the regulator node necessary for the core power. |
| 105 | |
| 106 | "#gpio-cells": |
| 107 | const: 2 |
| 108 | |
| 109 | gpio-controller: |
| 110 | type: boolean |
| 111 | description: | |
| 112 | If defined, LED controller of the MT7530 switch will run on GPIO mode. |
| 113 | |
| 114 | There are 15 controllable pins. |
| 115 | port 0 LED 0..2 as GPIO 0..2 |
| 116 | port 1 LED 0..2 as GPIO 3..5 |
| 117 | port 2 LED 0..2 as GPIO 6..8 |
| 118 | port 3 LED 0..2 as GPIO 9..11 |
| 119 | port 4 LED 0..2 as GPIO 12..14 |
| 120 | |
| 121 | "#interrupt-cells": |
| 122 | const: 1 |
| 123 | |
| 124 | interrupt-controller: true |
| 125 | |
| 126 | interrupts: |
| 127 | maxItems: 1 |
| 128 | |
| 129 | io-supply: |
| 130 | description: | |
| 131 | Phandle to the regulator node necessary for the I/O power. |
| 132 | See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for |
| 133 | details for the regulator setup on these boards. |
| 134 | |
| 135 | mediatek,mcm: |
| 136 | type: boolean |
| 137 | description: |
| 138 | Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 |
| 139 | switch is a part of the multi-chip module. |
| 140 | |
| 141 | reset-gpios: |
| 142 | description: | |
| 143 | GPIO to reset the switch. Use this if mediatek,mcm is not used. |
| 144 | This property is optional because some boards share the reset line with |
| 145 | other components which makes it impossible to probe the switch if the |
| 146 | reset line is used. |
| 147 | maxItems: 1 |
| 148 | |
| 149 | reset-names: |
| 150 | const: mcm |
| 151 | |
| 152 | resets: |
| 153 | description: |
| 154 | Phandle pointing to the system reset controller with line index for the |
| 155 | ethsys. |
| 156 | maxItems: 1 |
| 157 | |
| 158 | patternProperties: |
| 159 | "^(ethernet-)?ports$": |
| 160 | type: object |
| 161 | additionalProperties: true |
| 162 | |
| 163 | patternProperties: |
| 164 | "^(ethernet-)?port@[0-6]$": |
| 165 | type: object |
| 166 | additionalProperties: true |
| 167 | |
| 168 | properties: |
| 169 | reg: |
| 170 | description: |
| 171 | Port address described must be 5 or 6 for CPU port and from 0 to 5 |
| 172 | for user ports. |
| 173 | |
| 174 | allOf: |
| 175 | - if: |
| 176 | required: [ ethernet ] |
| 177 | then: |
| 178 | properties: |
| 179 | reg: |
| 180 | enum: |
| 181 | - 5 |
| 182 | - 6 |
| 183 | |
| 184 | required: |
| 185 | - compatible |
| 186 | - reg |
| 187 | |
| 188 | $defs: |
| 189 | mt7530-dsa-port: |
| 190 | patternProperties: |
| 191 | "^(ethernet-)?ports$": |
| 192 | patternProperties: |
| 193 | "^(ethernet-)?port@[0-6]$": |
| 194 | if: |
| 195 | required: [ ethernet ] |
| 196 | then: |
| 197 | if: |
| 198 | properties: |
| 199 | reg: |
| 200 | const: 5 |
| 201 | then: |
| 202 | properties: |
| 203 | phy-mode: |
| 204 | enum: |
| 205 | - gmii |
| 206 | - mii |
| 207 | - rgmii |
| 208 | else: |
| 209 | properties: |
| 210 | phy-mode: |
| 211 | enum: |
| 212 | - rgmii |
| 213 | - trgmii |
| 214 | |
| 215 | mt7531-dsa-port: |
| 216 | patternProperties: |
| 217 | "^(ethernet-)?ports$": |
| 218 | patternProperties: |
| 219 | "^(ethernet-)?port@[0-6]$": |
| 220 | if: |
| 221 | required: [ ethernet ] |
| 222 | then: |
| 223 | if: |
| 224 | properties: |
| 225 | reg: |
| 226 | const: 5 |
| 227 | then: |
| 228 | properties: |
| 229 | phy-mode: |
| 230 | enum: |
| 231 | - 1000base-x |
| 232 | - 2500base-x |
| 233 | - rgmii |
| 234 | - sgmii |
| 235 | else: |
| 236 | properties: |
| 237 | phy-mode: |
| 238 | enum: |
| 239 | - 1000base-x |
| 240 | - 2500base-x |
| 241 | - sgmii |
| 242 | |
| 243 | allOf: |
| 244 | - $ref: dsa.yaml#/$defs/ethernet-ports |
| 245 | - if: |
| 246 | required: |
| 247 | - mediatek,mcm |
| 248 | then: |
| 249 | properties: |
| 250 | reset-gpios: false |
| 251 | |
| 252 | required: |
| 253 | - resets |
| 254 | - reset-names |
| 255 | |
| 256 | - dependencies: |
| 257 | interrupt-controller: [ interrupts ] |
| 258 | |
| 259 | - if: |
| 260 | properties: |
| 261 | compatible: |
| 262 | const: mediatek,mt7530 |
| 263 | then: |
| 264 | $ref: "#/$defs/mt7530-dsa-port" |
| 265 | required: |
| 266 | - core-supply |
| 267 | - io-supply |
| 268 | |
| 269 | - if: |
| 270 | properties: |
| 271 | compatible: |
| 272 | const: mediatek,mt7531 |
| 273 | then: |
| 274 | $ref: "#/$defs/mt7531-dsa-port" |
| 275 | properties: |
| 276 | gpio-controller: false |
| 277 | mediatek,mcm: false |
| 278 | |
| 279 | - if: |
| 280 | properties: |
| 281 | compatible: |
| 282 | const: mediatek,mt7621 |
| 283 | then: |
| 284 | $ref: "#/$defs/mt7530-dsa-port" |
| 285 | required: |
| 286 | - mediatek,mcm |
| 287 | |
| 288 | - if: |
| 289 | properties: |
| 290 | compatible: |
Tom Rini | 9c8af15 | 2024-12-24 12:03:04 -0600 | [diff] [blame^] | 291 | enum: |
| 292 | - mediatek,mt7988-switch |
| 293 | - airoha,en7581-switch |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 294 | then: |
| 295 | $ref: "#/$defs/mt7530-dsa-port" |
| 296 | properties: |
| 297 | gpio-controller: false |
| 298 | mediatek,mcm: false |
| 299 | reset-names: false |
| 300 | |
| 301 | unevaluatedProperties: false |
| 302 | |
| 303 | examples: |
| 304 | # Example 1: Standalone MT7530 |
| 305 | - | |
| 306 | #include <dt-bindings/gpio/gpio.h> |
| 307 | |
| 308 | mdio { |
| 309 | #address-cells = <1>; |
| 310 | #size-cells = <0>; |
| 311 | |
| 312 | switch@1f { |
| 313 | compatible = "mediatek,mt7530"; |
| 314 | reg = <0x1f>; |
| 315 | |
| 316 | reset-gpios = <&pio 33 0>; |
| 317 | |
| 318 | core-supply = <&mt6323_vpa_reg>; |
| 319 | io-supply = <&mt6323_vemc3v3_reg>; |
| 320 | |
| 321 | ethernet-ports { |
| 322 | #address-cells = <1>; |
| 323 | #size-cells = <0>; |
| 324 | |
| 325 | port@0 { |
| 326 | reg = <0>; |
| 327 | label = "lan1"; |
| 328 | }; |
| 329 | |
| 330 | port@1 { |
| 331 | reg = <1>; |
| 332 | label = "lan2"; |
| 333 | }; |
| 334 | |
| 335 | port@2 { |
| 336 | reg = <2>; |
| 337 | label = "lan3"; |
| 338 | }; |
| 339 | |
| 340 | port@3 { |
| 341 | reg = <3>; |
| 342 | label = "lan4"; |
| 343 | }; |
| 344 | |
| 345 | port@4 { |
| 346 | reg = <4>; |
| 347 | label = "wan"; |
| 348 | }; |
| 349 | |
| 350 | port@6 { |
| 351 | reg = <6>; |
| 352 | ethernet = <&gmac0>; |
| 353 | phy-mode = "rgmii"; |
| 354 | |
| 355 | fixed-link { |
| 356 | speed = <1000>; |
| 357 | full-duplex; |
| 358 | pause; |
| 359 | }; |
| 360 | }; |
| 361 | }; |
| 362 | }; |
| 363 | }; |
| 364 | |
| 365 | # Example 2: MT7530 in MT7623AI SoC |
| 366 | - | |
| 367 | #include <dt-bindings/reset/mt2701-resets.h> |
| 368 | |
| 369 | mdio { |
| 370 | #address-cells = <1>; |
| 371 | #size-cells = <0>; |
| 372 | |
| 373 | switch@1f { |
| 374 | compatible = "mediatek,mt7530"; |
| 375 | reg = <0x1f>; |
| 376 | |
| 377 | mediatek,mcm; |
| 378 | resets = <ðsys MT2701_ETHSYS_MCM_RST>; |
| 379 | reset-names = "mcm"; |
| 380 | |
| 381 | core-supply = <&mt6323_vpa_reg>; |
| 382 | io-supply = <&mt6323_vemc3v3_reg>; |
| 383 | |
| 384 | ethernet-ports { |
| 385 | #address-cells = <1>; |
| 386 | #size-cells = <0>; |
| 387 | |
| 388 | port@0 { |
| 389 | reg = <0>; |
| 390 | label = "lan1"; |
| 391 | }; |
| 392 | |
| 393 | port@1 { |
| 394 | reg = <1>; |
| 395 | label = "lan2"; |
| 396 | }; |
| 397 | |
| 398 | port@2 { |
| 399 | reg = <2>; |
| 400 | label = "lan3"; |
| 401 | }; |
| 402 | |
| 403 | port@3 { |
| 404 | reg = <3>; |
| 405 | label = "lan4"; |
| 406 | }; |
| 407 | |
| 408 | port@4 { |
| 409 | reg = <4>; |
| 410 | label = "wan"; |
| 411 | }; |
| 412 | |
| 413 | port@6 { |
| 414 | reg = <6>; |
| 415 | ethernet = <&gmac0>; |
| 416 | phy-mode = "trgmii"; |
| 417 | |
| 418 | fixed-link { |
| 419 | speed = <1000>; |
| 420 | full-duplex; |
| 421 | pause; |
| 422 | }; |
| 423 | }; |
| 424 | }; |
| 425 | }; |
| 426 | }; |
| 427 | |
| 428 | # Example 3: Standalone MT7531 |
| 429 | - | |
| 430 | #include <dt-bindings/gpio/gpio.h> |
| 431 | #include <dt-bindings/interrupt-controller/irq.h> |
| 432 | |
| 433 | mdio { |
| 434 | #address-cells = <1>; |
| 435 | #size-cells = <0>; |
| 436 | |
| 437 | switch@0 { |
| 438 | compatible = "mediatek,mt7531"; |
| 439 | reg = <0>; |
| 440 | |
| 441 | reset-gpios = <&pio 54 0>; |
| 442 | |
| 443 | interrupt-controller; |
| 444 | #interrupt-cells = <1>; |
| 445 | interrupt-parent = <&pio>; |
| 446 | interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; |
| 447 | |
| 448 | ethernet-ports { |
| 449 | #address-cells = <1>; |
| 450 | #size-cells = <0>; |
| 451 | |
| 452 | port@0 { |
| 453 | reg = <0>; |
| 454 | label = "lan1"; |
| 455 | }; |
| 456 | |
| 457 | port@1 { |
| 458 | reg = <1>; |
| 459 | label = "lan2"; |
| 460 | }; |
| 461 | |
| 462 | port@2 { |
| 463 | reg = <2>; |
| 464 | label = "lan3"; |
| 465 | }; |
| 466 | |
| 467 | port@3 { |
| 468 | reg = <3>; |
| 469 | label = "lan4"; |
| 470 | }; |
| 471 | |
| 472 | port@4 { |
| 473 | reg = <4>; |
| 474 | label = "wan"; |
| 475 | }; |
| 476 | |
| 477 | port@6 { |
| 478 | reg = <6>; |
| 479 | ethernet = <&gmac0>; |
| 480 | phy-mode = "2500base-x"; |
| 481 | |
| 482 | fixed-link { |
| 483 | speed = <2500>; |
| 484 | full-duplex; |
| 485 | pause; |
| 486 | }; |
| 487 | }; |
| 488 | }; |
| 489 | }; |
| 490 | }; |
| 491 | |
| 492 | # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs |
| 493 | - | |
| 494 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 495 | #include <dt-bindings/reset/mt7621-reset.h> |
| 496 | |
| 497 | mdio { |
| 498 | #address-cells = <1>; |
| 499 | #size-cells = <0>; |
| 500 | |
| 501 | switch@1f { |
| 502 | compatible = "mediatek,mt7621"; |
| 503 | reg = <0x1f>; |
| 504 | |
| 505 | mediatek,mcm; |
| 506 | resets = <&sysc MT7621_RST_MCM>; |
| 507 | reset-names = "mcm"; |
| 508 | |
| 509 | interrupt-controller; |
| 510 | #interrupt-cells = <1>; |
| 511 | interrupt-parent = <&gic>; |
| 512 | interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
| 513 | |
| 514 | ethernet-ports { |
| 515 | #address-cells = <1>; |
| 516 | #size-cells = <0>; |
| 517 | |
| 518 | port@0 { |
| 519 | reg = <0>; |
| 520 | label = "lan1"; |
| 521 | }; |
| 522 | |
| 523 | port@1 { |
| 524 | reg = <1>; |
| 525 | label = "lan2"; |
| 526 | }; |
| 527 | |
| 528 | port@2 { |
| 529 | reg = <2>; |
| 530 | label = "lan3"; |
| 531 | }; |
| 532 | |
| 533 | port@3 { |
| 534 | reg = <3>; |
| 535 | label = "lan4"; |
| 536 | }; |
| 537 | |
| 538 | port@4 { |
| 539 | reg = <4>; |
| 540 | label = "wan"; |
| 541 | }; |
| 542 | |
| 543 | port@6 { |
| 544 | reg = <6>; |
| 545 | ethernet = <&gmac0>; |
| 546 | phy-mode = "trgmii"; |
| 547 | |
| 548 | fixed-link { |
| 549 | speed = <1000>; |
| 550 | full-duplex; |
| 551 | pause; |
| 552 | }; |
| 553 | }; |
| 554 | }; |
| 555 | }; |
| 556 | }; |
| 557 | |
| 558 | # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 |
| 559 | - | |
| 560 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 561 | #include <dt-bindings/reset/mt7621-reset.h> |
| 562 | |
| 563 | ethernet { |
| 564 | #address-cells = <1>; |
| 565 | #size-cells = <0>; |
| 566 | |
| 567 | pinctrl-names = "default"; |
| 568 | pinctrl-0 = <&rgmii2_pins>; |
| 569 | |
| 570 | mac@1 { |
| 571 | compatible = "mediatek,eth-mac"; |
| 572 | reg = <1>; |
| 573 | |
| 574 | phy-mode = "rgmii"; |
| 575 | phy-handle = <&example5_ethphy4>; |
| 576 | }; |
| 577 | |
| 578 | mdio { |
| 579 | #address-cells = <1>; |
| 580 | #size-cells = <0>; |
| 581 | |
| 582 | /* MT7530's phy4 */ |
| 583 | example5_ethphy4: ethernet-phy@4 { |
| 584 | reg = <4>; |
| 585 | }; |
| 586 | |
| 587 | switch@1f { |
| 588 | compatible = "mediatek,mt7621"; |
| 589 | reg = <0x1f>; |
| 590 | |
| 591 | mediatek,mcm; |
| 592 | resets = <&sysc MT7621_RST_MCM>; |
| 593 | reset-names = "mcm"; |
| 594 | |
| 595 | interrupt-controller; |
| 596 | #interrupt-cells = <1>; |
| 597 | interrupt-parent = <&gic>; |
| 598 | interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
| 599 | |
| 600 | ethernet-ports { |
| 601 | #address-cells = <1>; |
| 602 | #size-cells = <0>; |
| 603 | |
| 604 | port@0 { |
| 605 | reg = <0>; |
| 606 | label = "lan1"; |
| 607 | }; |
| 608 | |
| 609 | port@1 { |
| 610 | reg = <1>; |
| 611 | label = "lan2"; |
| 612 | }; |
| 613 | |
| 614 | port@2 { |
| 615 | reg = <2>; |
| 616 | label = "lan3"; |
| 617 | }; |
| 618 | |
| 619 | port@3 { |
| 620 | reg = <3>; |
| 621 | label = "lan4"; |
| 622 | }; |
| 623 | |
| 624 | /* Commented out, phy4 is connected to gmac1. |
| 625 | port@4 { |
| 626 | reg = <4>; |
| 627 | label = "wan"; |
| 628 | }; |
| 629 | */ |
| 630 | |
| 631 | port@6 { |
| 632 | reg = <6>; |
| 633 | ethernet = <&gmac0>; |
| 634 | phy-mode = "trgmii"; |
| 635 | |
| 636 | fixed-link { |
| 637 | speed = <1000>; |
| 638 | full-duplex; |
| 639 | pause; |
| 640 | }; |
| 641 | }; |
| 642 | }; |
| 643 | }; |
| 644 | }; |
| 645 | }; |
| 646 | |
| 647 | # Example 6: MT7621: mux external phy to SoC's gmac1 |
| 648 | - | |
| 649 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 650 | #include <dt-bindings/reset/mt7621-reset.h> |
| 651 | |
| 652 | ethernet { |
| 653 | #address-cells = <1>; |
| 654 | #size-cells = <0>; |
| 655 | |
| 656 | pinctrl-names = "default"; |
| 657 | pinctrl-0 = <&rgmii2_pins>; |
| 658 | |
| 659 | mac@1 { |
| 660 | compatible = "mediatek,eth-mac"; |
| 661 | reg = <1>; |
| 662 | |
| 663 | phy-mode = "rgmii"; |
| 664 | phy-handle = <&example6_ethphy7>; |
| 665 | }; |
| 666 | |
| 667 | mdio { |
| 668 | #address-cells = <1>; |
| 669 | #size-cells = <0>; |
| 670 | |
| 671 | /* External PHY */ |
| 672 | example6_ethphy7: ethernet-phy@7 { |
| 673 | reg = <7>; |
| 674 | phy-mode = "rgmii"; |
| 675 | }; |
| 676 | |
| 677 | switch@1f { |
| 678 | compatible = "mediatek,mt7621"; |
| 679 | reg = <0x1f>; |
| 680 | |
| 681 | mediatek,mcm; |
| 682 | resets = <&sysc MT7621_RST_MCM>; |
| 683 | reset-names = "mcm"; |
| 684 | |
| 685 | interrupt-controller; |
| 686 | #interrupt-cells = <1>; |
| 687 | interrupt-parent = <&gic>; |
| 688 | interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
| 689 | |
| 690 | ethernet-ports { |
| 691 | #address-cells = <1>; |
| 692 | #size-cells = <0>; |
| 693 | |
| 694 | port@0 { |
| 695 | reg = <0>; |
| 696 | label = "lan1"; |
| 697 | }; |
| 698 | |
| 699 | port@1 { |
| 700 | reg = <1>; |
| 701 | label = "lan2"; |
| 702 | }; |
| 703 | |
| 704 | port@2 { |
| 705 | reg = <2>; |
| 706 | label = "lan3"; |
| 707 | }; |
| 708 | |
| 709 | port@3 { |
| 710 | reg = <3>; |
| 711 | label = "lan4"; |
| 712 | }; |
| 713 | |
| 714 | port@4 { |
| 715 | reg = <4>; |
| 716 | label = "wan"; |
| 717 | }; |
| 718 | |
| 719 | port@6 { |
| 720 | reg = <6>; |
| 721 | ethernet = <&gmac0>; |
| 722 | phy-mode = "trgmii"; |
| 723 | |
| 724 | fixed-link { |
| 725 | speed = <1000>; |
| 726 | full-duplex; |
| 727 | pause; |
| 728 | }; |
| 729 | }; |
| 730 | }; |
| 731 | }; |
| 732 | }; |
| 733 | }; |
| 734 | |
| 735 | # Example 7: MT7621: mux external phy to MT7530's port 5 |
| 736 | - | |
| 737 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 738 | #include <dt-bindings/reset/mt7621-reset.h> |
| 739 | |
| 740 | ethernet { |
| 741 | #address-cells = <1>; |
| 742 | #size-cells = <0>; |
| 743 | |
| 744 | pinctrl-names = "default"; |
| 745 | pinctrl-0 = <&rgmii2_pins>; |
| 746 | |
| 747 | mdio { |
| 748 | #address-cells = <1>; |
| 749 | #size-cells = <0>; |
| 750 | |
| 751 | /* External PHY */ |
| 752 | example7_ethphy7: ethernet-phy@7 { |
| 753 | reg = <7>; |
| 754 | phy-mode = "rgmii"; |
| 755 | }; |
| 756 | |
| 757 | switch@1f { |
| 758 | compatible = "mediatek,mt7621"; |
| 759 | reg = <0x1f>; |
| 760 | |
| 761 | mediatek,mcm; |
| 762 | resets = <&sysc MT7621_RST_MCM>; |
| 763 | reset-names = "mcm"; |
| 764 | |
| 765 | interrupt-controller; |
| 766 | #interrupt-cells = <1>; |
| 767 | interrupt-parent = <&gic>; |
| 768 | interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
| 769 | |
| 770 | ethernet-ports { |
| 771 | #address-cells = <1>; |
| 772 | #size-cells = <0>; |
| 773 | |
| 774 | port@0 { |
| 775 | reg = <0>; |
| 776 | label = "lan1"; |
| 777 | }; |
| 778 | |
| 779 | port@1 { |
| 780 | reg = <1>; |
| 781 | label = "lan2"; |
| 782 | }; |
| 783 | |
| 784 | port@2 { |
| 785 | reg = <2>; |
| 786 | label = "lan3"; |
| 787 | }; |
| 788 | |
| 789 | port@3 { |
| 790 | reg = <3>; |
| 791 | label = "lan4"; |
| 792 | }; |
| 793 | |
| 794 | port@4 { |
| 795 | reg = <4>; |
| 796 | label = "wan"; |
| 797 | }; |
| 798 | |
| 799 | port@5 { |
| 800 | reg = <5>; |
| 801 | label = "extphy"; |
| 802 | phy-mode = "rgmii-txid"; |
| 803 | phy-handle = <&example7_ethphy7>; |
| 804 | }; |
| 805 | |
| 806 | port@6 { |
| 807 | reg = <6>; |
| 808 | ethernet = <&gmac0>; |
| 809 | phy-mode = "trgmii"; |
| 810 | |
| 811 | fixed-link { |
| 812 | speed = <1000>; |
| 813 | full-duplex; |
| 814 | pause; |
| 815 | }; |
| 816 | }; |
| 817 | }; |
| 818 | }; |
| 819 | }; |
| 820 | }; |