| Kevin Scholz | 521a4ef | 2019-10-07 19:26:36 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /********************************************************************** |
| 3 | * Copyright (C) 2012-2019 Cadence Design Systems, Inc. |
| 4 | ********************************************************************** |
| 5 | * WARNING: This file is auto-generated using api-generator utility. |
| 6 | * api-generator: 12.02.13bb8d5 |
| 7 | * Do not edit it manually. |
| 8 | ********************************************************************** |
| 9 | * Cadence Core Driver for LPDDR4. |
| 10 | ********************************************************************** |
| 11 | */ |
| 12 | #ifndef LPDDR4_STRUCTS_IF_H |
| 13 | #define LPDDR4_STRUCTS_IF_H |
| 14 | |
| 15 | #include <linux/types.h> |
| 16 | #include "lpddr4_if.h" |
| 17 | |
| 18 | /** @defgroup DataStructure Dynamic Data Structures |
| 19 | * This section defines the data structures used by the driver to provide |
| 20 | * hardware information, modification and dynamic operation of the driver. |
| 21 | * These data structures are defined in the header file of the core driver |
| 22 | * and utilized by the API. |
| 23 | * @{ |
| 24 | */ |
| 25 | |
| 26 | /********************************************************************** |
| 27 | * Structures and unions |
| 28 | **********************************************************************/ |
| 29 | /** |
| 30 | * Configuration of device. |
| 31 | * Object of this type is used for probe and init functions. |
| 32 | */ |
| 33 | struct lpddr4_config_s |
| 34 | { |
| 35 | /** Base address of controller registers */ |
| 36 | struct lpddr4_ctlregs_s* ctlbase; |
| 37 | /** Information/warning handler */ |
| 38 | lpddr4_infocallback infohandler; |
| 39 | /** Controller interrupt handler */ |
| 40 | lpddr4_ctlcallback ctlinterrupthandler; |
| 41 | /** PHY Independent Module interrupt handler */ |
| 42 | lpddr4_phyindepcallback phyindepinterrupthandler; |
| 43 | }; |
| 44 | |
| 45 | /** |
| 46 | * Structure contains private data for Core Driver that should not be used by |
| 47 | * upper layers. This is not a part of API and manipulating of those data may cause |
| 48 | * unpredictable behavior of Core Driver. |
| 49 | */ |
| 50 | struct lpddr4_privatedata_s |
| 51 | { |
| 52 | /** Base address of controller registers */ |
| 53 | struct lpddr4_ctlregs_s* ctlbase; |
| 54 | /** Information/warning handler */ |
| 55 | lpddr4_infocallback infohandler; |
| 56 | /** Controller interrupt handler */ |
| 57 | lpddr4_ctlcallback ctlinterrupthandler; |
| 58 | /** PHY Independent Module interrupt handler */ |
| 59 | lpddr4_phyindepcallback phyindepinterrupthandler; |
| 60 | }; |
| 61 | |
| 62 | /** Structure to contain debug information reported by the driver. */ |
| 63 | struct lpddr4_debuginfo_s |
| 64 | { |
| 65 | /** PLL Lock error. */ |
| 66 | bool pllerror; |
| 67 | /** I/O calibration error. */ |
| 68 | bool iocaliberror; |
| 69 | /** RX offset error. */ |
| 70 | bool rxoffseterror; |
| 71 | /** CA training error. */ |
| 72 | bool catraingerror; |
| 73 | /** Write levelling error. */ |
| 74 | bool wrlvlerror; |
| 75 | /** Gate Level error. */ |
| 76 | bool gatelvlerror; |
| 77 | /** Read Level error. */ |
| 78 | bool readlvlerror; |
| 79 | /** Write DQ training error. */ |
| 80 | bool dqtrainingerror; |
| 81 | }; |
| 82 | |
| 83 | /** Frequency Set Point mode register values */ |
| 84 | struct lpddr4_fspmoderegs_s |
| 85 | { |
| 86 | /** MR1 register data for the FSP. */ |
| 87 | uint8_t mr1data_fn[LPDDR4_MAX_CS]; |
| 88 | /** MR2 register data for the FSP. */ |
| 89 | uint8_t mr2data_fn[LPDDR4_MAX_CS]; |
| 90 | /** MR3 register data for the FSP. */ |
| 91 | uint8_t mr3data_fn[LPDDR4_MAX_CS]; |
| 92 | /** MR11 register data for the FSP. */ |
| 93 | uint8_t mr11data_fn[LPDDR4_MAX_CS]; |
| 94 | /** MR12 register data for the FSP. */ |
| 95 | uint8_t mr12data_fn[LPDDR4_MAX_CS]; |
| 96 | /** MR13 register data for the FSP. */ |
| 97 | uint8_t mr13data_fn[LPDDR4_MAX_CS]; |
| 98 | /** MR14 register data for the FSP. */ |
| 99 | uint8_t mr14data_fn[LPDDR4_MAX_CS]; |
| 100 | /** MR22 register data for the selected frequency. */ |
| 101 | uint8_t mr22data_fn[LPDDR4_MAX_CS]; |
| 102 | }; |
| 103 | |
| 104 | /** Structure to hold data set to initalise registers. */ |
| 105 | struct lpddr4_reginitdata_s |
| 106 | { |
| 107 | /** Register initialisation data for the Controller. */ |
| 108 | uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT]; |
| 109 | /** Should be set to true, if the corresponding denaliCtlReg element has been updated. */ |
| 110 | bool updatectlreg[LPDDR4_CTL_REG_COUNT]; |
| 111 | /** Register initialisation data for PHY independent module. */ |
| 112 | uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT]; |
| 113 | /** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */ |
| 114 | bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT]; |
| 115 | /** Register initialisation data for the PHY. */ |
| 116 | uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT]; |
| 117 | /** Should be set to true, if the corresponding denaliPhyReg element has been updated. */ |
| 118 | bool updatephyreg[LPDDR4_PHY_REG_COUNT]; |
| 119 | }; |
| 120 | |
| 121 | #endif /* LPDDR4_STRUCTS_IF_H */ |