Pragnesh Patel | 1cfbd7a | 2020-11-14 14:42:34 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * ocores-i2c.c: I2C bus driver for OpenCores I2C controller |
| 4 | * (https://opencores.org/projects/i2c) |
| 5 | * |
| 6 | * (C) Copyright Peter Korsgaard <peter@korsgaard.com> |
| 7 | * |
| 8 | * Copyright (C) 2020 SiFive, Inc. |
| 9 | * Pragnesh Patel <pragnesh.patel@sifive.com> |
| 10 | * |
| 11 | * Support for the GRLIB port of the controller by |
| 12 | * Andreas Larsson <andreas@gaisler.com> |
| 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <clk.h> |
| 18 | #include <dm.h> |
| 19 | #include <dm/device_compat.h> |
| 20 | #include <i2c.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/compat.h> |
| 23 | #include <linux/log2.h> |
| 24 | #include <linux/delay.h> |
| 25 | |
| 26 | /* registers */ |
| 27 | #define OCI2C_PRELOW 0 |
| 28 | #define OCI2C_PREHIGH 1 |
| 29 | #define OCI2C_CONTROL 2 |
| 30 | #define OCI2C_DATA 3 |
| 31 | #define OCI2C_CMD 4 /* write only */ |
| 32 | #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ |
| 33 | |
| 34 | #define OCI2C_CTRL_IEN 0x40 |
| 35 | #define OCI2C_CTRL_EN 0x80 |
| 36 | |
| 37 | #define OCI2C_CMD_START 0x91 |
| 38 | #define OCI2C_CMD_STOP 0x41 |
| 39 | #define OCI2C_CMD_READ 0x21 |
| 40 | #define OCI2C_CMD_WRITE 0x11 |
| 41 | #define OCI2C_CMD_READ_ACK 0x21 |
| 42 | #define OCI2C_CMD_READ_NACK 0x29 |
| 43 | #define OCI2C_CMD_IACK 0x01 |
| 44 | |
| 45 | #define OCI2C_STAT_IF 0x01 |
| 46 | #define OCI2C_STAT_TIP 0x02 |
| 47 | #define OCI2C_STAT_ARBLOST 0x20 |
| 48 | #define OCI2C_STAT_BUSY 0x40 |
| 49 | #define OCI2C_STAT_NACK 0x80 |
| 50 | |
| 51 | #define STATE_DONE 0 |
| 52 | #define STATE_START 1 |
| 53 | #define STATE_WRITE 2 |
| 54 | #define STATE_READ 3 |
| 55 | #define STATE_ERROR 4 |
| 56 | |
| 57 | #define TYPE_OCORES 0 |
| 58 | #define TYPE_GRLIB 1 |
| 59 | |
| 60 | #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ |
| 61 | |
| 62 | struct ocores_i2c_bus { |
| 63 | void __iomem *base; |
| 64 | u32 reg_shift; |
| 65 | u32 reg_io_width; |
| 66 | unsigned long flags; |
| 67 | struct i2c_msg *msg; |
| 68 | int pos; |
| 69 | int nmsgs; |
| 70 | int state; /* see STATE_ */ |
| 71 | struct clk clk; |
| 72 | int ip_clk_khz; |
| 73 | int bus_clk_khz; |
| 74 | void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value); |
| 75 | u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg); |
| 76 | }; |
| 77 | |
| 78 | DECLARE_GLOBAL_DATA_PTR; |
| 79 | |
| 80 | /* Boolean attribute values */ |
| 81 | enum { |
| 82 | FALSE = 0, |
| 83 | TRUE, |
| 84 | }; |
| 85 | |
| 86 | static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 87 | { |
| 88 | writeb(value, i2c->base + (reg << i2c->reg_shift)); |
| 89 | } |
| 90 | |
| 91 | static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 92 | { |
| 93 | writew(value, i2c->base + (reg << i2c->reg_shift)); |
| 94 | } |
| 95 | |
| 96 | static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 97 | { |
| 98 | writel(value, i2c->base + (reg << i2c->reg_shift)); |
| 99 | } |
| 100 | |
| 101 | static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 102 | { |
| 103 | out_be16(i2c->base + (reg << i2c->reg_shift), value); |
| 104 | } |
| 105 | |
| 106 | static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 107 | { |
| 108 | out_be32(i2c->base + (reg << i2c->reg_shift), value); |
| 109 | } |
| 110 | |
| 111 | static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg) |
| 112 | { |
| 113 | return readb(i2c->base + (reg << i2c->reg_shift)); |
| 114 | } |
| 115 | |
| 116 | static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg) |
| 117 | { |
| 118 | return readw(i2c->base + (reg << i2c->reg_shift)); |
| 119 | } |
| 120 | |
| 121 | static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg) |
| 122 | { |
| 123 | return readl(i2c->base + (reg << i2c->reg_shift)); |
| 124 | } |
| 125 | |
| 126 | static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg) |
| 127 | { |
| 128 | return in_be16(i2c->base + (reg << i2c->reg_shift)); |
| 129 | } |
| 130 | |
| 131 | static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg) |
| 132 | { |
| 133 | return in_be32(i2c->base + (reg << i2c->reg_shift)); |
| 134 | } |
| 135 | |
| 136 | static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 137 | { |
| 138 | i2c->setreg(i2c, reg, value); |
| 139 | } |
| 140 | |
| 141 | static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg) |
| 142 | { |
| 143 | return i2c->getreg(i2c, reg); |
| 144 | } |
| 145 | |
| 146 | static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg) |
| 147 | { |
| 148 | return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0); |
| 149 | } |
| 150 | |
| 151 | static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat) |
| 152 | { |
| 153 | struct i2c_msg *msg = i2c->msg; |
| 154 | |
| 155 | if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { |
| 156 | /* stop has been sent */ |
| 157 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); |
| 158 | return; |
| 159 | } |
| 160 | |
| 161 | /* error? */ |
| 162 | if (stat & OCI2C_STAT_ARBLOST) { |
| 163 | i2c->state = STATE_ERROR; |
| 164 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
| 165 | return; |
| 166 | } |
| 167 | |
| 168 | if (i2c->state == STATE_START || i2c->state == STATE_WRITE) { |
| 169 | i2c->state = |
| 170 | (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; |
| 171 | |
| 172 | if (stat & OCI2C_STAT_NACK) { |
| 173 | i2c->state = STATE_ERROR; |
| 174 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
| 175 | return; |
| 176 | } |
| 177 | } else { |
| 178 | msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); |
| 179 | } |
| 180 | |
| 181 | /* end of msg? */ |
| 182 | if (i2c->pos == msg->len) { |
| 183 | i2c->nmsgs--; |
| 184 | i2c->msg++; |
| 185 | i2c->pos = 0; |
| 186 | msg = i2c->msg; |
| 187 | |
| 188 | if (i2c->nmsgs) { /* end? */ |
| 189 | /* send start? */ |
| 190 | if (!(msg->flags & I2C_M_NOSTART)) { |
| 191 | u8 addr = i2c_8bit_addr_from_msg(msg); |
| 192 | |
| 193 | i2c->state = STATE_START; |
| 194 | |
| 195 | oc_setreg(i2c, OCI2C_DATA, addr); |
| 196 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); |
| 197 | return; |
| 198 | } |
| 199 | i2c->state = (msg->flags & I2C_M_RD) |
| 200 | ? STATE_READ : STATE_WRITE; |
| 201 | } else { |
| 202 | i2c->state = STATE_DONE; |
| 203 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
| 204 | return; |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | if (i2c->state == STATE_READ) { |
| 209 | oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ? |
| 210 | OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); |
| 211 | } else { |
| 212 | oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); |
| 213 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | static irqreturn_t ocores_isr(int irq, void *dev_id) |
| 218 | { |
| 219 | struct ocores_i2c_bus *i2c = dev_id; |
| 220 | u8 stat = oc_getreg(i2c, OCI2C_STATUS); |
| 221 | |
| 222 | if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) { |
| 223 | if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY)) |
| 224 | return IRQ_NONE; |
| 225 | } else if (!(stat & OCI2C_STAT_IF)) { |
| 226 | return IRQ_NONE; |
| 227 | } |
| 228 | ocores_process(i2c, stat); |
| 229 | |
| 230 | return IRQ_HANDLED; |
| 231 | } |
| 232 | |
| 233 | /** |
| 234 | * Wait until something change in a given register |
| 235 | * @i2c: ocores I2C device instance |
| 236 | * @reg: register to query |
| 237 | * @mask: bitmask to apply on register value |
| 238 | * @val: expected result |
| 239 | * @msec: timeout in msec |
| 240 | * |
| 241 | * Timeout is necessary to avoid to stay here forever when the chip |
| 242 | * does not answer correctly. |
| 243 | * |
| 244 | * Return: 0 on success, -ETIMEDOUT on timeout |
| 245 | */ |
| 246 | static int ocores_wait(struct ocores_i2c_bus *i2c, |
| 247 | int reg, u8 mask, u8 val, |
| 248 | const unsigned long msec) |
| 249 | { |
| 250 | u32 count = 0; |
| 251 | |
| 252 | while (1) { |
| 253 | u8 status = oc_getreg(i2c, reg); |
| 254 | |
| 255 | if ((status & mask) == val) |
| 256 | break; |
| 257 | |
| 258 | udelay(1); |
| 259 | count += 1; |
| 260 | |
| 261 | if (count == (1000 * msec)) |
| 262 | return -ETIMEDOUT; |
| 263 | } |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * Wait until is possible to process some data |
| 269 | * @i2c: ocores I2C device instance |
| 270 | * |
| 271 | * Used when the device is in polling mode (interrupts disabled). |
| 272 | * |
| 273 | * Return: 0 on success, -ETIMEDOUT on timeout |
| 274 | */ |
| 275 | static int ocores_poll_wait(struct ocores_i2c_bus *i2c) |
| 276 | { |
| 277 | u8 mask; |
| 278 | int err; |
| 279 | |
| 280 | if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { |
| 281 | /* transfer is over */ |
| 282 | mask = OCI2C_STAT_BUSY; |
| 283 | } else { |
| 284 | /* on going transfer */ |
| 285 | mask = OCI2C_STAT_TIP; |
| 286 | /* |
| 287 | * We wait for the data to be transferred (8bit), |
| 288 | * then we start polling on the ACK/NACK bit |
| 289 | */ |
| 290 | udelay((8 * 1000) / i2c->bus_clk_khz); |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * once we are here we expect to get the expected result immediately |
| 295 | * so if after 1ms we timeout then something is broken. |
| 296 | */ |
| 297 | err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1); |
| 298 | if (err) |
| 299 | debug("%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", |
| 300 | __func__, mask); |
| 301 | return err; |
| 302 | } |
| 303 | |
| 304 | /** |
| 305 | * It handles an IRQ-less transfer |
| 306 | * @i2c: ocores I2C device instance |
| 307 | * |
| 308 | * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same |
| 309 | * (only that IRQ are not produced). This means that we can re-use entirely |
| 310 | * ocores_isr(), we just add our polling code around it. |
| 311 | * |
| 312 | * It can run in atomic context |
| 313 | */ |
| 314 | static void ocores_process_polling(struct ocores_i2c_bus *i2c) |
| 315 | { |
| 316 | while (1) { |
| 317 | irqreturn_t ret; |
| 318 | int err; |
| 319 | |
| 320 | err = ocores_poll_wait(i2c); |
| 321 | if (err) { |
| 322 | i2c->state = STATE_ERROR; |
| 323 | break; /* timeout */ |
| 324 | } |
| 325 | |
| 326 | ret = ocores_isr(-1, i2c); |
| 327 | if (ret == IRQ_NONE) { |
| 328 | break; /* all messages have been transferred */ |
| 329 | } else { |
| 330 | if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) |
| 331 | if (i2c->state == STATE_DONE) |
| 332 | break; |
| 333 | } |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | static int ocores_xfer_core(struct ocores_i2c_bus *i2c, |
| 338 | struct i2c_msg *msgs, int num, bool polling) |
| 339 | { |
| 340 | u8 ctrl; |
| 341 | |
| 342 | ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
| 343 | |
| 344 | if (polling) |
| 345 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); |
| 346 | |
| 347 | i2c->msg = msgs; |
| 348 | i2c->pos = 0; |
| 349 | i2c->nmsgs = num; |
| 350 | i2c->state = STATE_START; |
| 351 | |
| 352 | oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); |
| 353 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); |
| 354 | |
| 355 | if (polling) |
| 356 | ocores_process_polling(i2c); |
| 357 | |
| 358 | return (i2c->state == STATE_DONE) ? num : -EIO; |
| 359 | } |
| 360 | |
| 361 | static int ocores_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) |
| 362 | { |
| 363 | struct ocores_i2c_bus *bus = dev_get_priv(dev); |
| 364 | int ret; |
| 365 | |
| 366 | debug("i2c_xfer: %d messages\n", nmsgs); |
| 367 | |
| 368 | ret = ocores_xfer_core(bus, msg, nmsgs, 1); |
| 369 | |
| 370 | if (ret != nmsgs) { |
| 371 | debug("i2c_write: error sending\n"); |
| 372 | return -EREMOTEIO; |
| 373 | } |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | static int ocores_i2c_enable_clk(struct udevice *dev) |
| 379 | { |
| 380 | struct ocores_i2c_bus *bus = dev_get_priv(dev); |
| 381 | ulong clk_rate; |
| 382 | int ret; |
| 383 | |
| 384 | ret = clk_get_by_index(dev, 0, &bus->clk); |
| 385 | if (ret) |
| 386 | return -EINVAL; |
| 387 | |
| 388 | ret = clk_enable(&bus->clk); |
| 389 | if (ret) |
| 390 | return ret; |
| 391 | |
| 392 | clk_rate = clk_get_rate(&bus->clk); |
| 393 | if (!clk_rate) |
| 394 | return -EINVAL; |
| 395 | |
| 396 | bus->ip_clk_khz = clk_rate / 1000; |
| 397 | |
| 398 | clk_free(&bus->clk); |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | static int ocores_init(struct udevice *dev, struct ocores_i2c_bus *bus) |
| 404 | { |
| 405 | int prescale; |
| 406 | int diff; |
| 407 | u8 ctrl = oc_getreg(bus, OCI2C_CONTROL); |
| 408 | |
| 409 | /* make sure the device is disabled */ |
| 410 | ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); |
| 411 | oc_setreg(bus, OCI2C_CONTROL, ctrl); |
| 412 | |
| 413 | prescale = (bus->ip_clk_khz / (5 * bus->bus_clk_khz)) - 1; |
| 414 | prescale = clamp(prescale, 0, 0xffff); |
| 415 | |
| 416 | diff = bus->ip_clk_khz / (5 * (prescale + 1)) - bus->bus_clk_khz; |
| 417 | if (abs(diff) > bus->bus_clk_khz / 10) { |
| 418 | debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n", |
| 419 | bus->ip_clk_khz, bus->bus_clk_khz); |
| 420 | return -EINVAL; |
| 421 | } |
| 422 | |
| 423 | oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff); |
| 424 | oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8); |
| 425 | |
| 426 | /* Init the device */ |
| 427 | oc_setreg(bus, OCI2C_CMD, OCI2C_CMD_IACK); |
| 428 | oc_setreg(bus, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); |
| 429 | |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | /* |
| 434 | * Read and write functions for the GRLIB port of the controller. Registers are |
| 435 | * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one |
| 436 | * register. The subsequent registers have their offsets decreased accordingly. |
| 437 | */ |
| 438 | static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg) |
| 439 | { |
| 440 | u32 rd; |
| 441 | int rreg = reg; |
| 442 | |
| 443 | if (reg != OCI2C_PRELOW) |
| 444 | rreg--; |
| 445 | rd = in_be32(i2c->base + (rreg << i2c->reg_shift)); |
| 446 | if (reg == OCI2C_PREHIGH) |
| 447 | return (u8)(rd >> 8); |
| 448 | else |
| 449 | return (u8)rd; |
| 450 | } |
| 451 | |
| 452 | static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value) |
| 453 | { |
| 454 | u32 curr, wr; |
| 455 | int rreg = reg; |
| 456 | |
| 457 | if (reg != OCI2C_PRELOW) |
| 458 | rreg--; |
| 459 | if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { |
| 460 | curr = in_be32(i2c->base + (rreg << i2c->reg_shift)); |
| 461 | if (reg == OCI2C_PRELOW) |
| 462 | wr = (curr & 0xff00) | value; |
| 463 | else |
| 464 | wr = (((u32)value) << 8) | (curr & 0xff); |
| 465 | } else { |
| 466 | wr = value; |
| 467 | } |
| 468 | out_be32(i2c->base + (rreg << i2c->reg_shift), wr); |
| 469 | } |
| 470 | |
| 471 | static int ocores_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) |
| 472 | { |
| 473 | int prescale; |
| 474 | int diff; |
| 475 | struct ocores_i2c_bus *bus = dev_get_priv(dev); |
| 476 | |
| 477 | /* speed in Khz */ |
| 478 | speed = speed / 1000; |
| 479 | |
| 480 | prescale = (bus->ip_clk_khz / (5 * speed)) - 1; |
| 481 | prescale = clamp(prescale, 0, 0xffff); |
| 482 | |
| 483 | diff = bus->ip_clk_khz / (5 * (prescale + 1)) - speed; |
| 484 | if (abs(diff) > speed / 10) { |
| 485 | debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n", |
| 486 | bus->ip_clk_khz, speed); |
| 487 | return -EINVAL; |
| 488 | } |
| 489 | |
| 490 | oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff); |
| 491 | oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8); |
| 492 | |
| 493 | bus->bus_clk_khz = speed; |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | int ocores_i2c_get_bus_speed(struct udevice *dev) |
| 498 | { |
| 499 | struct ocores_i2c_bus *bus = dev_get_priv(dev); |
| 500 | |
| 501 | return (bus->bus_clk_khz * 1000); |
| 502 | } |
| 503 | |
| 504 | static const struct dm_i2c_ops ocores_i2c_ops = { |
| 505 | .xfer = ocores_i2c_xfer, |
| 506 | .set_bus_speed = ocores_i2c_set_bus_speed, |
| 507 | .get_bus_speed = ocores_i2c_get_bus_speed, |
| 508 | }; |
| 509 | |
| 510 | static int ocores_i2c_probe(struct udevice *dev) |
| 511 | { |
| 512 | struct ocores_i2c_bus *bus = dev_get_priv(dev); |
| 513 | bool clock_frequency_present; |
| 514 | u32 val; |
| 515 | u32 clock_frequency_khz; |
| 516 | int ret; |
| 517 | |
| 518 | bus->base = (void __iomem *)devfdt_get_addr(dev); |
| 519 | |
| 520 | if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) { |
| 521 | /* no 'reg-shift', check for deprecated 'regstep' */ |
| 522 | ret = dev_read_u32(dev, "regstep", &val); |
| 523 | if (ret) { |
| 524 | dev_err(dev, |
| 525 | "missing both reg-shift and regstep property: %d\n", ret); |
| 526 | return -EINVAL; |
| 527 | } else { |
| 528 | bus->reg_shift = ilog2(val); |
| 529 | dev_warn(dev, |
| 530 | "regstep property deprecated, use reg-shift\n"); |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | if (dev_read_u32(dev, "clock-frequency", &val)) { |
| 535 | bus->bus_clk_khz = 100; |
| 536 | clock_frequency_present = FALSE; |
| 537 | } else { |
| 538 | bus->bus_clk_khz = val / 1000; |
| 539 | clock_frequency_khz = val / 1000; |
| 540 | clock_frequency_present = TRUE; |
| 541 | } |
| 542 | |
| 543 | ret = ocores_i2c_enable_clk(dev); |
| 544 | if (ret) |
| 545 | return ret; |
| 546 | |
| 547 | if (bus->ip_clk_khz == 0) { |
| 548 | if (dev_read_u32(dev, "opencores,ip-clock-frequency", &val)) { |
| 549 | if (!clock_frequency_present) { |
| 550 | dev_err(dev, |
| 551 | "Missing required parameter 'opencores,ip-clock-frequency'\n"); |
| 552 | clk_disable(&bus->clk); |
| 553 | return -ENODEV; |
| 554 | } |
| 555 | |
| 556 | bus->ip_clk_khz = clock_frequency_khz; |
| 557 | dev_warn(dev, |
| 558 | "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); |
| 559 | } else { |
| 560 | bus->ip_clk_khz = val / 1000; |
| 561 | if (clock_frequency_present) |
| 562 | bus->bus_clk_khz = clock_frequency_khz; |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | bus->reg_io_width = dev_read_u32_default(dev, "reg-io-width", 1); |
| 567 | |
| 568 | if (dev_get_driver_data(dev) == TYPE_GRLIB) { |
| 569 | debug("GRLIB variant of i2c-ocores\n"); |
| 570 | bus->setreg = oc_setreg_grlib; |
| 571 | bus->getreg = oc_getreg_grlib; |
| 572 | } |
| 573 | |
| 574 | if (!bus->setreg || !bus->getreg) { |
| 575 | bool be = (cpu_to_be32(0x12345678) == 0x12345678); |
| 576 | |
| 577 | switch (bus->reg_io_width) { |
| 578 | case 1: |
| 579 | bus->setreg = oc_setreg_8; |
| 580 | bus->getreg = oc_getreg_8; |
| 581 | break; |
| 582 | |
| 583 | case 2: |
| 584 | bus->setreg = be ? oc_setreg_16be : oc_setreg_16; |
| 585 | bus->getreg = be ? oc_getreg_16be : oc_getreg_16; |
| 586 | break; |
| 587 | |
| 588 | case 4: |
| 589 | bus->setreg = be ? oc_setreg_32be : oc_setreg_32; |
| 590 | bus->getreg = be ? oc_getreg_32be : oc_getreg_32; |
| 591 | break; |
| 592 | |
| 593 | default: |
| 594 | debug("Unsupported I/O width (%d)\n", |
| 595 | bus->reg_io_width); |
| 596 | ret = -EINVAL; |
| 597 | goto err_clk; |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | /* |
| 602 | * Set OCORES_FLAG_BROKEN_IRQ to enable workaround for |
| 603 | * FU540-C000 SoC in polling mode. |
| 604 | * Since the SoC does have an interrupt, its DT has an interrupt |
| 605 | * property - But this should be bypassed as the IRQ logic in this |
| 606 | * SoC is broken. |
| 607 | */ |
| 608 | |
| 609 | if (device_is_compatible(dev, "sifive,fu540-c000-i2c")) |
| 610 | bus->flags |= OCORES_FLAG_BROKEN_IRQ; |
| 611 | |
| 612 | ret = ocores_init(dev, bus); |
| 613 | if (ret) |
| 614 | goto err_clk; |
| 615 | |
| 616 | return 0; |
| 617 | |
| 618 | err_clk: |
| 619 | clk_disable(&bus->clk); |
| 620 | return ret; |
| 621 | } |
| 622 | |
| 623 | static const struct udevice_id ocores_i2c_ids[] = { |
| 624 | { .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES }, |
| 625 | { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB }, |
| 626 | { .compatible = "sifive,fu540-c000-i2c" }, |
| 627 | { .compatible = "sifive,i2c0" }, |
| 628 | }; |
| 629 | |
| 630 | U_BOOT_DRIVER(i2c_ocores) = { |
| 631 | .name = "i2c_ocores", |
| 632 | .id = UCLASS_I2C, |
| 633 | .of_match = ocores_i2c_ids, |
| 634 | .probe = ocores_i2c_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 635 | .priv_auto = sizeof(struct ocores_i2c_bus), |
Pragnesh Patel | 1cfbd7a | 2020-11-14 14:42:34 +0530 | [diff] [blame] | 636 | .ops = &ocores_i2c_ops, |
| 637 | }; |