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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01007
Simon Glassb2c1cac2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070013
Simon Glassfef72b72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070036 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070040 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020041 fdt-dummy0 = "/translation-test@8000/dev@0,0";
42 fdt-dummy1 = "/translation-test@8000/dev@1,100";
43 fdt-dummy2 = "/translation-test@8000/dev@2,200";
44 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060045 usb0 = &usb_0;
46 usb1 = &usb_1;
47 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020048 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020049 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060050 };
51
Simon Glassed96cde2018-12-10 10:37:33 -070052 audio: audio-codec {
53 compatible = "sandbox,audio-codec";
54 #sound-dai-cells = <1>;
55 };
56
Philippe Reynes1ee26482020-07-24 18:19:51 +020057 buttons {
58 compatible = "gpio-keys";
59
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020060 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020061 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020062 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020063 };
64
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020065 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020066 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020067 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020068 };
69 };
70
Simon Glassc953aaf2018-12-10 10:37:34 -070071 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060072 reg = <0 0>;
73 compatible = "google,cros-ec-sandbox";
74
75 /*
76 * This describes the flash memory within the EC. Note
77 * that the STM32L flash erases to 0, not 0xff.
78 */
79 flash {
80 image-pos = <0x08000000>;
81 size = <0x20000>;
82 erase-value = <0>;
83
84 /* Information for sandbox */
85 ro {
86 image-pos = <0>;
87 size = <0xf000>;
88 };
89 wp-ro {
90 image-pos = <0xf000>;
91 size = <0x1000>;
92 };
93 rw {
94 image-pos = <0x10000>;
95 size = <0x10000>;
96 };
97 };
98 };
99
Yannick Fertré9712c822019-10-07 15:29:05 +0200100 dsi_host: dsi_host {
101 compatible = "sandbox,dsi-host";
102 };
103
Simon Glassb2c1cac2014-02-26 15:59:21 -0700104 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600105 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700106 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600107 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700108 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600109 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100110 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
111 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700112 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100113 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
114 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
115 <&gpio_b 7 GPIO_IN 3 2 1>,
116 <&gpio_b 8 GPIO_OUT 3 2 1>,
117 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100118 test3-gpios =
119 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
120 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
121 <&gpio_c 2 GPIO_OUT>,
122 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
123 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200124 <&gpio_c 5 GPIO_IN>,
125 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
126 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530127 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
128 test5-gpios = <&gpio_a 19>;
129
Simon Glass6df01f92018-12-10 10:37:37 -0700130 int-value = <1234>;
131 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200132 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200133 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600134 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700135 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600136 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200137 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530138
139 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
140 <&muxcontroller0 2>, <&muxcontroller0 3>,
141 <&muxcontroller1>;
142 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
143 mux-syscon = <&syscon3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700144 };
145
146 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600147 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700148 compatible = "not,compatible";
149 };
150
151 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600152 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700153 };
154
Simon Glass5620cf82018-10-01 12:22:40 -0600155 backlight: backlight {
156 compatible = "pwm-backlight";
157 enable-gpios = <&gpio_a 1>;
158 power-supply = <&ldo_1>;
159 pwms = <&pwm 0 1000>;
160 default-brightness-level = <5>;
161 brightness-levels = <0 16 32 64 128 170 202 234 255>;
162 };
163
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200164 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200165 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200166 bind-test-child1 {
167 compatible = "sandbox,phy";
168 #phy-cells = <1>;
169 };
170
171 bind-test-child2 {
172 compatible = "simple-bus";
173 };
174 };
175
Simon Glassb2c1cac2014-02-26 15:59:21 -0700176 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600177 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700178 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600179 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700180 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530181
182 mux-controls = <&muxcontroller0 0>;
183 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700184 };
185
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200186 phy_provider0: gen_phy@0 {
187 compatible = "sandbox,phy";
188 #phy-cells = <1>;
189 };
190
191 phy_provider1: gen_phy@1 {
192 compatible = "sandbox,phy";
193 #phy-cells = <0>;
194 broken;
195 };
196
developer71092972020-05-02 11:35:12 +0200197 phy_provider2: gen_phy@2 {
198 compatible = "sandbox,phy";
199 #phy-cells = <0>;
200 };
201
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200202 gen_phy_user: gen_phy_user {
203 compatible = "simple-bus";
204 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
205 phy-names = "phy1", "phy2", "phy3";
206 };
207
developer71092972020-05-02 11:35:12 +0200208 gen_phy_user1: gen_phy_user1 {
209 compatible = "simple-bus";
210 phys = <&phy_provider0 0>, <&phy_provider2>;
211 phy-names = "phy1", "phy2";
212 };
213
Simon Glassb2c1cac2014-02-26 15:59:21 -0700214 some-bus {
215 #address-cells = <1>;
216 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600217 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600218 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600219 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700220 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600221 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700222 compatible = "denx,u-boot-fdt-test";
223 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600224 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700225 ping-add = <5>;
226 };
Simon Glass40717422014-07-23 06:55:18 -0600227 c-test@0 {
228 compatible = "denx,u-boot-fdt-test";
229 reg = <0>;
230 ping-expect = <6>;
231 ping-add = <6>;
232 };
233 c-test@1 {
234 compatible = "denx,u-boot-fdt-test";
235 reg = <1>;
236 ping-expect = <7>;
237 ping-add = <7>;
238 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700239 };
240
241 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600242 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600243 ping-expect = <6>;
244 ping-add = <6>;
245 compatible = "google,another-fdt-test";
246 };
247
248 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600249 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600250 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700251 ping-add = <6>;
252 compatible = "google,another-fdt-test";
253 };
254
Simon Glass0ccb0972015-01-25 08:27:05 -0700255 f-test {
256 compatible = "denx,u-boot-fdt-test";
257 };
258
259 g-test {
260 compatible = "denx,u-boot-fdt-test";
261 };
262
Bin Mengd9d24782018-10-10 22:07:01 -0700263 h-test {
264 compatible = "denx,u-boot-fdt-test1";
265 };
266
developercf8bc132020-05-02 11:35:10 +0200267 i-test {
268 compatible = "mediatek,u-boot-fdt-test";
269 #address-cells = <1>;
270 #size-cells = <0>;
271
272 subnode@0 {
273 reg = <0>;
274 };
275
276 subnode@1 {
277 reg = <1>;
278 };
279
280 subnode@2 {
281 reg = <2>;
282 };
283 };
284
Simon Glass204675c2019-12-29 21:19:25 -0700285 devres-test {
286 compatible = "denx,u-boot-devres-test";
287 };
288
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530289 another-test {
290 reg = <0 2>;
291 compatible = "denx,u-boot-fdt-test";
292 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
293 test5-gpios = <&gpio_a 19>;
294 };
295
Simon Glass3c601b12020-07-07 13:12:06 -0600296 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600297 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600298 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600299 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600300 child {
301 compatible = "denx,u-boot-acpi-test";
302 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600303 };
304
Simon Glass3c601b12020-07-07 13:12:06 -0600305 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600306 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600307 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600308 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600309 };
310
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200311 clocks {
312 clk_fixed: clk-fixed {
313 compatible = "fixed-clock";
314 #clock-cells = <0>;
315 clock-frequency = <1234>;
316 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000317
318 clk_fixed_factor: clk-fixed-factor {
319 compatible = "fixed-factor-clock";
320 #clock-cells = <0>;
321 clock-div = <3>;
322 clock-mult = <2>;
323 clocks = <&clk_fixed>;
324 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200325
326 osc {
327 compatible = "fixed-clock";
328 #clock-cells = <0>;
329 clock-frequency = <20000000>;
330 };
Stephen Warrena9622432016-06-17 09:44:00 -0600331 };
332
333 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600334 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600335 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200336 assigned-clocks = <&clk_sandbox 3>;
337 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600338 };
339
340 clk-test {
341 compatible = "sandbox,clk-test";
342 clocks = <&clk_fixed>,
343 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200344 <&clk_sandbox 0>,
345 <&clk_sandbox 3>,
346 <&clk_sandbox 2>;
347 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600348 };
349
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200350 ccf: clk-ccf {
351 compatible = "sandbox,clk-ccf";
352 };
353
Simon Glass5b968632015-05-22 15:42:15 -0600354 eth@10002000 {
355 compatible = "sandbox,eth";
356 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500357 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600358 };
359
360 eth_5: eth@10003000 {
361 compatible = "sandbox,eth";
362 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500363 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600364 };
365
Bin Meng04a11cb2015-08-27 22:25:53 -0700366 eth_3: sbe5 {
367 compatible = "sandbox,eth";
368 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500369 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700370 };
371
Simon Glass5b968632015-05-22 15:42:15 -0600372 eth@10004000 {
373 compatible = "sandbox,eth";
374 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500375 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600376 };
377
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700378 firmware {
379 sandbox_firmware: sandbox-firmware {
380 compatible = "sandbox,firmware";
381 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200382
383 sandbox-scmi-agent@0 {
384 compatible = "sandbox,scmi-agent";
385 #address-cells = <1>;
386 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200387
388 clk_scmi0: protocol@14 {
389 reg = <0x14>;
390 #clock-cells = <1>;
391 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200392
393 reset_scmi0: protocol@16 {
394 reg = <0x16>;
395 #reset-cells = <1>;
396 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200397 };
398
399 sandbox-scmi-agent@1 {
400 compatible = "sandbox,scmi-agent";
401 #address-cells = <1>;
402 #size-cells = <0>;
403
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200404 clk_scmi1: protocol@14 {
405 reg = <0x14>;
406 #clock-cells = <1>;
407 };
408
Etienne Carriere02fd1262020-09-09 18:44:00 +0200409 protocol@10 {
410 reg = <0x10>;
411 };
412 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700413 };
414
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100415 pinctrl-gpio {
416 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700417
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100418 gpio_a: base-gpios {
419 compatible = "sandbox,gpio";
420 gpio-controller;
421 #gpio-cells = <1>;
422 gpio-bank-name = "a";
423 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200424 hog_input_active_low {
425 gpio-hog;
426 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200427 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200428 };
429 hog_input_active_high {
430 gpio-hog;
431 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200432 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200433 };
434 hog_output_low {
435 gpio-hog;
436 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200437 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200438 };
439 hog_output_high {
440 gpio-hog;
441 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200442 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200443 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100444 };
445
446 gpio_b: extra-gpios {
447 compatible = "sandbox,gpio";
448 gpio-controller;
449 #gpio-cells = <5>;
450 gpio-bank-name = "b";
451 sandbox,gpio-count = <10>;
452 };
Simon Glass25348a42014-10-13 23:42:11 -0600453
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100454 gpio_c: pinmux-gpios {
455 compatible = "sandbox,gpio";
456 gpio-controller;
457 #gpio-cells = <2>;
458 gpio-bank-name = "c";
459 sandbox,gpio-count = <10>;
460 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100461 };
462
Simon Glass7df766e2014-12-10 08:55:55 -0700463 i2c@0 {
464 #address-cells = <1>;
465 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600466 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700467 compatible = "sandbox,i2c";
468 clock-frequency = <100000>;
469 eeprom@2c {
470 reg = <0x2c>;
471 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700472 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200473 partitions {
474 compatible = "fixed-partitions";
475 #address-cells = <1>;
476 #size-cells = <1>;
477 bootcount_i2c: bootcount@10 {
478 reg = <10 2>;
479 };
480 };
Simon Glass7df766e2014-12-10 08:55:55 -0700481 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200482
Simon Glass336b2952015-05-22 15:42:17 -0600483 rtc_0: rtc@43 {
484 reg = <0x43>;
485 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700486 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600487 };
488
489 rtc_1: rtc@61 {
490 reg = <0x61>;
491 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700492 sandbox,emul = <&emul1>;
493 };
494
495 i2c_emul: emul {
496 reg = <0xff>;
497 compatible = "sandbox,i2c-emul-parent";
498 emul_eeprom: emul-eeprom {
499 compatible = "sandbox,i2c-eeprom";
500 sandbox,filename = "i2c.bin";
501 sandbox,size = <256>;
502 };
503 emul0: emul0 {
504 compatible = "sandbox,i2c-rtc";
505 };
506 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600507 compatible = "sandbox,i2c-rtc";
508 };
509 };
510
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200511 sandbox_pmic: sandbox_pmic {
512 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700513 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200514 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200515
516 mc34708: pmic@41 {
517 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700518 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200519 };
Simon Glass7df766e2014-12-10 08:55:55 -0700520 };
521
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100522 bootcount@0 {
523 compatible = "u-boot,bootcount-rtc";
524 rtc = <&rtc_1>;
525 offset = <0x13>;
526 };
527
Michal Simek4f18f922020-05-28 11:48:55 +0200528 bootcount {
529 compatible = "u-boot,bootcount-i2c-eeprom";
530 i2c-eeprom = <&bootcount_i2c>;
531 };
532
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100533 adc@0 {
534 compatible = "sandbox,adc";
535 vdd-supply = <&buck2>;
536 vss-microvolts = <0>;
537 };
538
Simon Glass515dcff2020-02-06 09:55:00 -0700539 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700540 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700541 interrupt-controller;
542 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700543 };
544
Simon Glass90b6fef2016-01-18 19:52:26 -0700545 lcd {
546 u-boot,dm-pre-reloc;
547 compatible = "sandbox,lcd-sdl";
548 xres = <1366>;
549 yres = <768>;
550 };
551
Simon Glassd783eb32015-07-06 12:54:34 -0600552 leds {
553 compatible = "gpio-leds";
554
555 iracibble {
556 gpios = <&gpio_a 1 0>;
557 label = "sandbox:red";
558 };
559
560 martinet {
561 gpios = <&gpio_a 2 0>;
562 label = "sandbox:green";
563 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200564
565 default_on {
566 gpios = <&gpio_a 5 0>;
567 label = "sandbox:default_on";
568 default-state = "on";
569 };
570
571 default_off {
572 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400573 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200574 default-state = "off";
575 };
Simon Glassd783eb32015-07-06 12:54:34 -0600576 };
577
Stephen Warren62f2c902016-05-16 17:41:37 -0600578 mbox: mbox {
579 compatible = "sandbox,mbox";
580 #mbox-cells = <1>;
581 };
582
583 mbox-test {
584 compatible = "sandbox,mbox-test";
585 mboxes = <&mbox 100>, <&mbox 1>;
586 mbox-names = "other", "test";
587 };
588
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900589 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400590 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900591 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400592 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900593 compatible = "sandbox,cpu_sandbox";
594 u-boot,dm-pre-reloc;
595 };
Mario Sixdea5df72018-08-06 10:23:44 +0200596
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900597 cpu-test2 {
598 compatible = "sandbox,cpu_sandbox";
599 u-boot,dm-pre-reloc;
600 };
Mario Sixdea5df72018-08-06 10:23:44 +0200601
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900602 cpu-test3 {
603 compatible = "sandbox,cpu_sandbox";
604 u-boot,dm-pre-reloc;
605 };
Mario Sixdea5df72018-08-06 10:23:44 +0200606 };
607
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500608 chipid: chipid {
609 compatible = "sandbox,soc";
610 };
611
Simon Glassc953aaf2018-12-10 10:37:34 -0700612 i2s: i2s {
613 compatible = "sandbox,i2s";
614 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700615 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700616 };
617
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200618 nop-test_0 {
619 compatible = "sandbox,nop_sandbox1";
620 nop-test_1 {
621 compatible = "sandbox,nop_sandbox2";
622 bind = "True";
623 };
624 nop-test_2 {
625 compatible = "sandbox,nop_sandbox2";
626 bind = "False";
627 };
628 };
629
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200630 misc-test {
631 compatible = "sandbox,misc_sandbox";
632 };
633
Simon Glasse4fef742017-04-23 20:02:07 -0600634 mmc2 {
635 compatible = "sandbox,mmc";
636 };
637
638 mmc1 {
639 compatible = "sandbox,mmc";
640 };
641
642 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600643 compatible = "sandbox,mmc";
644 };
645
Simon Glass53a68b32019-02-16 20:24:50 -0700646 pch {
647 compatible = "sandbox,pch";
648 };
649
Tom Rini4a3ca482020-02-11 12:41:23 -0500650 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700651 compatible = "sandbox,pci";
652 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500653 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700654 #address-cells = <3>;
655 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600656 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700657 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700658 pci@0,0 {
659 compatible = "pci-generic";
660 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600661 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700662 };
Alex Margineanf1274432019-06-07 11:24:24 +0300663 pci@1,0 {
664 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600665 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
666 reg = <0x02000814 0 0 0 0
667 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600668 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300669 };
Simon Glass937bb472019-12-06 21:41:57 -0700670 p2sb-pci@2,0 {
671 compatible = "sandbox,p2sb";
672 reg = <0x02001010 0 0 0 0>;
673 sandbox,emul = <&p2sb_emul>;
674
675 adder {
676 intel,p2sb-port-id = <3>;
677 compatible = "sandbox,adder";
678 };
679 };
Simon Glass8c501022019-12-06 21:41:54 -0700680 pci@1e,0 {
681 compatible = "sandbox,pmc";
682 reg = <0xf000 0 0 0 0>;
683 sandbox,emul = <&pmc_emul1e>;
684 acpi-base = <0x400>;
685 gpe0-dwx-mask = <0xf>;
686 gpe0-dwx-shift-base = <4>;
687 gpe0-dw = <6 7 9>;
688 gpe0-sts = <0x20>;
689 gpe0-en = <0x30>;
690 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700691 pci@1f,0 {
692 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600693 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
694 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600695 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700696 };
697 };
698
Simon Glassb98ba4c2019-09-25 08:56:10 -0600699 pci-emul0 {
700 compatible = "sandbox,pci-emul-parent";
701 swap_case_emul0_0: emul0@0,0 {
702 compatible = "sandbox,swap-case";
703 };
704 swap_case_emul0_1: emul0@1,0 {
705 compatible = "sandbox,swap-case";
706 use-ea;
707 };
708 swap_case_emul0_1f: emul0@1f,0 {
709 compatible = "sandbox,swap-case";
710 };
Simon Glass937bb472019-12-06 21:41:57 -0700711 p2sb_emul: emul@2,0 {
712 compatible = "sandbox,p2sb-emul";
713 };
Simon Glass8c501022019-12-06 21:41:54 -0700714 pmc_emul1e: emul@1e,0 {
715 compatible = "sandbox,pmc-emul";
716 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600717 };
718
Tom Rini4a3ca482020-02-11 12:41:23 -0500719 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700720 compatible = "sandbox,pci";
721 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500722 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700723 #address-cells = <3>;
724 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700725 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
726 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
727 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700728 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200729 0x0c 0x00 0x1234 0x5678
730 0x10 0x00 0x1234 0x5678>;
731 pci@10,0 {
732 reg = <0x8000 0 0 0 0>;
733 };
Bin Meng408e5902018-08-03 01:14:41 -0700734 };
735
Tom Rini4a3ca482020-02-11 12:41:23 -0500736 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700737 compatible = "sandbox,pci";
738 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500739 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700740 #address-cells = <3>;
741 #size-cells = <2>;
742 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
743 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
744 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
745 pci@1f,0 {
746 compatible = "pci-generic";
747 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600748 sandbox,emul = <&swap_case_emul2_1f>;
749 };
750 };
751
752 pci-emul2 {
753 compatible = "sandbox,pci-emul-parent";
754 swap_case_emul2_1f: emul2@1f,0 {
755 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700756 };
757 };
758
Ramon Friedc64f19b2019-04-27 11:15:23 +0300759 pci_ep: pci_ep {
760 compatible = "sandbox,pci_ep";
761 };
762
Simon Glass9c433fe2017-04-23 20:10:44 -0600763 probing {
764 compatible = "simple-bus";
765 test1 {
766 compatible = "denx,u-boot-probe-test";
767 };
768
769 test2 {
770 compatible = "denx,u-boot-probe-test";
771 };
772
773 test3 {
774 compatible = "denx,u-boot-probe-test";
775 };
776
777 test4 {
778 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100779 first-syscon = <&syscon0>;
780 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100781 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600782 };
783 };
784
Stephen Warren92c67fa2016-07-13 13:45:31 -0600785 pwrdom: power-domain {
786 compatible = "sandbox,power-domain";
787 #power-domain-cells = <1>;
788 };
789
790 power-domain-test {
791 compatible = "sandbox,power-domain-test";
792 power-domains = <&pwrdom 2>;
793 };
794
Simon Glass5620cf82018-10-01 12:22:40 -0600795 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600796 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600797 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600798 };
799
800 pwm2 {
801 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600802 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600803 };
804
Simon Glass3d355e62015-07-06 12:54:31 -0600805 ram {
806 compatible = "sandbox,ram";
807 };
808
Simon Glassd860f222015-07-06 12:54:29 -0600809 reset@0 {
810 compatible = "sandbox,warm-reset";
811 };
812
813 reset@1 {
814 compatible = "sandbox,reset";
815 };
816
Stephen Warren6488e642016-06-17 09:43:59 -0600817 resetc: reset-ctl {
818 compatible = "sandbox,reset-ctl";
819 #reset-cells = <1>;
820 };
821
822 reset-ctl-test {
823 compatible = "sandbox,reset-ctl-test";
824 resets = <&resetc 100>, <&resetc 2>;
825 reset-names = "other", "test";
826 };
827
Sughosh Ganu23e37512019-12-28 23:58:31 +0530828 rng {
829 compatible = "sandbox,sandbox-rng";
830 };
831
Nishanth Menonedf85812015-09-17 15:42:41 -0500832 rproc_1: rproc@1 {
833 compatible = "sandbox,test-processor";
834 remoteproc-name = "remoteproc-test-dev1";
835 };
836
837 rproc_2: rproc@2 {
838 compatible = "sandbox,test-processor";
839 internal-memory-mapped;
840 remoteproc-name = "remoteproc-test-dev2";
841 };
842
Simon Glass5620cf82018-10-01 12:22:40 -0600843 panel {
844 compatible = "simple-panel";
845 backlight = <&backlight 0 100>;
846 };
847
Ramon Fried26ed32e2018-07-02 02:57:59 +0300848 smem@0 {
849 compatible = "sandbox,smem";
850 };
851
Simon Glass76072ac2018-12-10 10:37:36 -0700852 sound {
853 compatible = "sandbox,sound";
854 cpu {
855 sound-dai = <&i2s 0>;
856 };
857
858 codec {
859 sound-dai = <&audio 0>;
860 };
861 };
862
Simon Glass25348a42014-10-13 23:42:11 -0600863 spi@0 {
864 #address-cells = <1>;
865 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600866 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600867 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +0200868 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass25348a42014-10-13 23:42:11 -0600869 spi.bin@0 {
870 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000871 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600872 spi-max-frequency = <40000000>;
873 sandbox,filename = "spi.bin";
874 };
Ovidiu Panaitae734732020-12-14 19:06:47 +0200875 spi.bin@1 {
876 reg = <1>;
877 compatible = "spansion,m25p16", "jedec,spi-nor";
878 spi-max-frequency = <50000000>;
879 sandbox,filename = "spi.bin";
880 spi-cpol;
881 spi-cpha;
882 };
Simon Glass25348a42014-10-13 23:42:11 -0600883 };
884
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100885 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600886 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200887 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600888 };
889
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100890 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600891 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600892 reg = <0x20 5
893 0x28 6
894 0x30 7
895 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600896 };
897
Patrick Delaunayee010432019-03-07 09:57:13 +0100898 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900899 compatible = "simple-mfd", "syscon";
900 reg = <0x40 5
901 0x48 6
902 0x50 7
903 0x58 8>;
904 };
905
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530906 syscon3: syscon@3 {
907 compatible = "simple-mfd", "syscon";
908 reg = <0x000100 0x10>;
909
910 muxcontroller0: a-mux-controller {
911 compatible = "mmio-mux";
912 #mux-control-cells = <1>;
913
914 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
915 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
916 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
917 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
918 u-boot,mux-autoprobe;
919 };
920 };
921
922 muxcontroller1: emul-mux-controller {
923 compatible = "mux-emul";
924 #mux-control-cells = <0>;
925 u-boot,mux-autoprobe;
926 idle-state = <0xabcd>;
927 };
928
Simon Glass791a17f2020-12-16 21:20:27 -0700929 testfdtm0 {
930 compatible = "denx,u-boot-fdtm-test";
931 };
932
933 testfdtm1: testfdtm1 {
934 compatible = "denx,u-boot-fdtm-test";
935 };
936
937 testfdtm2 {
938 compatible = "denx,u-boot-fdtm-test";
939 };
940
Sean Anderson79d3bba2020-09-28 10:52:23 -0400941 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800942 compatible = "sandbox,timer";
943 clock-frequency = <1000000>;
944 };
945
Sean Anderson79d3bba2020-09-28 10:52:23 -0400946 timer@1 {
947 compatible = "sandbox,timer";
948 sandbox,timebase-frequency-fallback;
949 };
950
Miquel Raynal80938c12018-05-15 11:57:27 +0200951 tpm2 {
952 compatible = "sandbox,tpm2";
953 };
954
Simon Glass5b968632015-05-22 15:42:15 -0600955 uart0: serial {
956 compatible = "sandbox,serial";
957 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500958 };
959
Simon Glass31680482015-03-25 12:23:05 -0600960 usb_0: usb@0 {
961 compatible = "sandbox,usb";
962 status = "disabled";
963 hub {
964 compatible = "sandbox,usb-hub";
965 #address-cells = <1>;
966 #size-cells = <0>;
967 flash-stick {
968 reg = <0>;
969 compatible = "sandbox,usb-flash";
970 };
971 };
972 };
973
974 usb_1: usb@1 {
975 compatible = "sandbox,usb";
976 hub {
977 compatible = "usb-hub";
978 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +0200979 #address-cells = <1>;
980 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -0600981 hub-emul {
982 compatible = "sandbox,usb-hub";
983 #address-cells = <1>;
984 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700985 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600986 reg = <0>;
987 compatible = "sandbox,usb-flash";
988 sandbox,filepath = "testflash.bin";
989 };
990
Simon Glass4700fe52015-11-08 23:48:01 -0700991 flash-stick@1 {
992 reg = <1>;
993 compatible = "sandbox,usb-flash";
994 sandbox,filepath = "testflash1.bin";
995 };
996
997 flash-stick@2 {
998 reg = <2>;
999 compatible = "sandbox,usb-flash";
1000 sandbox,filepath = "testflash2.bin";
1001 };
1002
Simon Glassc0ccc722015-11-08 23:48:08 -07001003 keyb@3 {
1004 reg = <3>;
1005 compatible = "sandbox,usb-keyb";
1006 };
1007
Simon Glass31680482015-03-25 12:23:05 -06001008 };
Michael Walle7c961322020-06-02 01:47:07 +02001009
1010 usbstor@1 {
1011 reg = <1>;
1012 };
1013 usbstor@3 {
1014 reg = <3>;
1015 };
Simon Glass31680482015-03-25 12:23:05 -06001016 };
1017 };
1018
1019 usb_2: usb@2 {
1020 compatible = "sandbox,usb";
1021 status = "disabled";
1022 };
1023
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001024 spmi: spmi@0 {
1025 compatible = "sandbox,spmi";
1026 #address-cells = <0x1>;
1027 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001028 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001029 pm8916@0 {
1030 compatible = "qcom,spmi-pmic";
1031 reg = <0x0 0x1>;
1032 #address-cells = <0x1>;
1033 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001034 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001035
1036 spmi_gpios: gpios@c000 {
1037 compatible = "qcom,pm8916-gpio";
1038 reg = <0xc000 0x400>;
1039 gpio-controller;
1040 gpio-count = <4>;
1041 #gpio-cells = <2>;
1042 gpio-bank-name="spmi";
1043 };
1044 };
1045 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001046
1047 wdt0: wdt@0 {
1048 compatible = "sandbox,wdt";
1049 };
Rob Clarka471b672018-01-10 11:33:30 +01001050
Mario Six95922152018-08-09 14:51:19 +02001051 axi: axi@0 {
1052 compatible = "sandbox,axi";
1053 #address-cells = <0x1>;
1054 #size-cells = <0x1>;
1055 store@0 {
1056 compatible = "sandbox,sandbox_store";
1057 reg = <0x0 0x400>;
1058 };
1059 };
1060
Rob Clarka471b672018-01-10 11:33:30 +01001061 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001062 #address-cells = <1>;
1063 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001064 setting = "sunrise ohoka";
1065 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001066 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001067 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001068 chosen-test {
1069 compatible = "denx,u-boot-fdt-test";
1070 reg = <9 1>;
1071 };
1072 };
Mario Six35616ef2018-03-12 14:53:33 +01001073
1074 translation-test@8000 {
1075 compatible = "simple-bus";
1076 reg = <0x8000 0x4000>;
1077
1078 #address-cells = <0x2>;
1079 #size-cells = <0x1>;
1080
1081 ranges = <0 0x0 0x8000 0x1000
1082 1 0x100 0x9000 0x1000
1083 2 0x200 0xA000 0x1000
1084 3 0x300 0xB000 0x1000
1085 >;
1086
Fabien Dessenne22236e02019-05-31 15:11:30 +02001087 dma-ranges = <0 0x000 0x10000000 0x1000
1088 1 0x100 0x20000000 0x1000
1089 >;
1090
Mario Six35616ef2018-03-12 14:53:33 +01001091 dev@0,0 {
1092 compatible = "denx,u-boot-fdt-dummy";
1093 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001094 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001095 };
1096
1097 dev@1,100 {
1098 compatible = "denx,u-boot-fdt-dummy";
1099 reg = <1 0x100 0x1000>;
1100
1101 };
1102
1103 dev@2,200 {
1104 compatible = "denx,u-boot-fdt-dummy";
1105 reg = <2 0x200 0x1000>;
1106 };
1107
1108
1109 noxlatebus@3,300 {
1110 compatible = "simple-bus";
1111 reg = <3 0x300 0x1000>;
1112
1113 #address-cells = <0x1>;
1114 #size-cells = <0x0>;
1115
1116 dev@42 {
1117 compatible = "denx,u-boot-fdt-dummy";
1118 reg = <0x42>;
1119 };
1120 };
1121 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001122
1123 osd {
1124 compatible = "sandbox,sandbox_osd";
1125 };
Tom Rinib93eea72018-09-30 18:16:51 -04001126
Jens Wiklander86afaa62018-09-25 16:40:16 +02001127 sandbox_tee {
1128 compatible = "sandbox,tee";
1129 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001130
1131 sandbox_virtio1 {
1132 compatible = "sandbox,virtio1";
1133 };
1134
1135 sandbox_virtio2 {
1136 compatible = "sandbox,virtio2";
1137 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001138
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001139 sandbox_scmi {
1140 compatible = "sandbox,scmi-devices";
1141 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001142 resets = <&reset_scmi0 3>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001143 };
1144
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001145 pinctrl {
1146 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001147
Sean Anderson3438e3b2020-09-14 11:01:57 -04001148 pinctrl-names = "default", "alternate";
1149 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1150 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001151
Sean Anderson3438e3b2020-09-14 11:01:57 -04001152 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001153 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001154 pins = "P5";
1155 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001156 bias-pull-up;
1157 input-disable;
1158 };
1159 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001160 pins = "P6";
1161 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001162 output-high;
1163 drive-open-drain;
1164 };
1165 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001166 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001167 bias-pull-down;
1168 input-enable;
1169 };
1170 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001171 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001172 bias-disable;
1173 };
1174 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001175
1176 pinctrl_i2c: i2c {
1177 groups {
1178 groups = "I2C_UART";
1179 function = "I2C";
1180 };
1181
1182 pins {
1183 pins = "P0", "P1";
1184 drive-open-drain;
1185 };
1186 };
1187
1188 pinctrl_i2s: i2s {
1189 groups = "SPI_I2S";
1190 function = "I2S";
1191 };
1192
1193 pinctrl_spi: spi {
1194 groups = "SPI_I2S";
1195 function = "SPI";
1196
1197 cs {
1198 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1199 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1200 };
1201 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001202 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001203
1204 hwspinlock@0 {
1205 compatible = "sandbox,hwspinlock";
1206 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001207
1208 dma: dma {
1209 compatible = "sandbox,dma";
1210 #dma-cells = <1>;
1211
1212 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1213 dma-names = "m2m", "tx0", "rx0";
1214 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001215
Alex Marginean0649be52019-07-12 10:13:53 +03001216 /*
1217 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1218 * end of the test. If parent mdio is removed first, clean-up of the
1219 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1220 * active at the end of the test. That it turn doesn't allow the mdio
1221 * class to be destroyed, triggering an error.
1222 */
1223 mdio-mux-test {
1224 compatible = "sandbox,mdio-mux";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 mdio-parent-bus = <&mdio>;
1228
1229 mdio-ch-test@0 {
1230 reg = <0>;
1231 };
1232 mdio-ch-test@1 {
1233 reg = <1>;
1234 };
1235 };
1236
1237 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001238 compatible = "sandbox,mdio";
1239 };
Sean Andersonb7860542020-06-24 06:41:12 -04001240
1241 pm-bus-test {
1242 compatible = "simple-pm-bus";
1243 clocks = <&clk_sandbox 4>;
1244 power-domains = <&pwrdom 1>;
1245 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001246
1247 resetc2: syscon-reset {
1248 compatible = "syscon-reset";
1249 #reset-cells = <1>;
1250 regmap = <&syscon0>;
1251 offset = <1>;
1252 mask = <0x27FFFFFF>;
1253 assert-high = <0>;
1254 };
1255
1256 syscon-reset-test {
1257 compatible = "sandbox,misc_sandbox";
1258 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1259 reset-names = "valid", "no_mask", "out_of_range";
1260 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301261
Simon Glass458b66a2020-11-05 06:32:05 -07001262 sysinfo {
1263 compatible = "sandbox,sysinfo-sandbox";
1264 };
1265
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301266 some_regmapped-bus {
1267 #address-cells = <0x1>;
1268 #size-cells = <0x1>;
1269
1270 ranges = <0x0 0x0 0x10>;
1271 compatible = "simple-bus";
1272
1273 regmap-test_0 {
1274 reg = <0 0x10>;
1275 compatible = "sandbox,regmap_test";
1276 };
1277 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001278};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001279
1280#include "sandbox_pmic.dtsi"