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git01.mediatek.com / filogic / uboot / 9c6d33cdc0b51c44eb02774dbdd8ab1b14cc436a / . / arch / arm / include / asm / spl.h
blob: 5c5d33f0bdac78c8c6a68098adafc599eed56341 [file] [log] [blame]
Tom Rini29d69dc2012-08-14 08:50:58 -0700[diff] [blame]1/*
2 * (C) Copyright 2012
3 * Texas Instruments, <www.ti.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Tom Rini29d69dc2012-08-14 08:50:58 -0700[diff] [blame]6 */
7#ifndef _ASM_SPL_H_
8#define _ASM_SPL_H_
9
Marek Vasutea0123c2014-10-16 12:25:40 +0200[diff] [blame]10#if defined(CONFIG_OMAP) \
Masahiro Yamada74726562014-04-23 21:20:43 +0900[diff] [blame]11 || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
12 || defined(CONFIG_EXYNOS4210)
Tom Rini29d69dc2012-08-14 08:50:58 -0700[diff] [blame]13/* Platform-specific defines */
14#include <asm/arch/spl.h>
15
Masahiro Yamada74726562014-04-23 21:20:43 +0900[diff] [blame]16#else
17enum {
18 BOOT_DEVICE_RAM,
19 BOOT_DEVICE_MMC1,
20 BOOT_DEVICE_MMC2,
21 BOOT_DEVICE_MMC2_2,
22 BOOT_DEVICE_NAND,
23 BOOT_DEVICE_ONENAND,
24 BOOT_DEVICE_NOR,
25 BOOT_DEVICE_UART,
26 BOOT_DEVICE_SPI,
27 BOOT_DEVICE_SATA,
28 BOOT_DEVICE_I2C,
Simon Glass040d8182015-02-07 10:47:29 -0700[diff] [blame]29 BOOT_DEVICE_BOARD,
Masahiro Yamada74726562014-04-23 21:20:43 +0900[diff] [blame]30 BOOT_DEVICE_NONE
31};
32#endif
33
Nikita Kiryanov33eefe42015-11-08 17:11:49 +0200[diff] [blame]34/**
35 * Board specific load method for boards that have a special way of loading
36 * U-Boot, which does not fit with the existing SPL code.
37 *
38 * @return 0 on success, negative errno value on failure.
39 */
40
41int spl_board_load_image(void);
Simon Glass040d8182015-02-07 10:47:29 -0700[diff] [blame]42
Tom Rini31dfba42012-08-22 15:31:05 -0700[diff] [blame]43/* Linker symbols. */
Simon Glassed70c8f2013-03-14 06:54:53 +0000[diff] [blame]44extern char __bss_start[], __bss_end[];
Tom Rini31dfba42012-08-22 15:31:05 -0700[diff] [blame]45
Simon Glassaeca9cc2015-03-03 08:02:58 -0700[diff] [blame]46#ifndef CONFIG_DM
Tom Rini31dfba42012-08-22 15:31:05 -0700[diff] [blame]47extern gd_t gdata;
Simon Glassaeca9cc2015-03-03 08:02:58 -0700[diff] [blame]48#endif
Tom Rini31dfba42012-08-22 15:31:05 -0700[diff] [blame]49
Tom Rini29d69dc2012-08-14 08:50:58 -0700[diff] [blame]50#endif