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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +09002/*
3 * Configuation settings for the sh7757lcr board
4 *
5 * Copyright (C) 2011 Renesas Solutions Corp.
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +09006 */
7
8#ifndef __SH7757LCR_H
9#define __SH7757LCR_H
10
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090011#define CONFIG_CPU_SH7757 1
Nobuhiro Iwamatsu67395912011-10-31 13:16:02 +090012#define CONFIG_SH7757LCR_DDR_ECC 1
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090013
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020014#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090015
16/* MEMORY */
17#define SH7757LCR_SDRAM_BASE (0x80000000)
18#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
19#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
20#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
21
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090022#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090023#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
24
25/* SCIF */
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090026#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090027
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090028#undef CONFIG_SYS_LOADS_BAUD_CHANGE
29
30#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
31#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
32#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
33 (128 + 16) * 1024 * 1024)
34
35#define CONFIG_SYS_MONITOR_BASE 0x00000000
36#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
37#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
38#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
39
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090040/* Ether */
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090041#define CONFIG_SH_ETHER_USE_PORT 0
42#define CONFIG_SH_ETHER_PHY_ADDR 1
43#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
Yoshihiro Shimoda86671632011-10-11 18:11:03 +090044#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsu32f900e2012-05-16 10:23:21 +090045#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090046
47#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
48#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
49#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
50#define SH7757LCR_ETHERNET_MAC_SIZE 17
51#define SH7757LCR_ETHERNET_NUM_CH 2
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090052
53/* Gigabit Ether */
54#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
55
56/* SPI */
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090057#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090058
Yoshihiro Shimoda6ff24942012-03-05 20:11:12 +000059/* MMCIF */
Yoshihiro Shimoda6ff24942012-03-05 20:11:12 +000060#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
61#define CONFIG_SH_MMCIF_CLK 48000000
62
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090063/* SH7757 board */
64#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
65#define SH7757LCR_GRA_OFFSET 0x1f000000
66#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
67#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
68#define SH7757LCR_PCIEBRG_ADDR 0x00090000
69#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
70
71/* ENV setting */
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090072#define CONFIG_EXTRA_ENV_SETTINGS \
73 "netboot=bootp; bootm\0"
74
75/* Board Clock */
76#define CONFIG_SYS_CLK_FREQ 48000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090077#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +090078#endif /* __SH7757LCR_H */