Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the sh7757lcr board |
| 4 | * |
| 5 | * Copyright (C) 2011 Renesas Solutions Corp. |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __SH7757LCR_H |
| 9 | #define __SH7757LCR_H |
| 10 | |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 11 | #define CONFIG_CPU_SH7757 1 |
Nobuhiro Iwamatsu | 6739591 | 2011-10-31 13:16:02 +0900 | [diff] [blame] | 12 | #define CONFIG_SH7757LCR_DDR_ECC 1 |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 13 | |
Vladimir Zapolskiy | 5e72b84 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 14 | #define CONFIG_DISPLAY_BOARDINFO |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 15 | |
| 16 | /* MEMORY */ |
| 17 | #define SH7757LCR_SDRAM_BASE (0x80000000) |
| 18 | #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) |
| 19 | #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ |
| 20 | #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) |
| 21 | |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 22 | #define CONFIG_SYS_PBSIZE 256 |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 23 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
| 24 | |
| 25 | /* SCIF */ |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 26 | #define CONFIG_CONS_SCIF2 1 |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 27 | |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 28 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
| 29 | |
| 30 | #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) |
| 31 | #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) |
| 32 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 33 | (128 + 16) * 1024 * 1024) |
| 34 | |
| 35 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 |
| 36 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| 37 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 38 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
| 39 | |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 40 | /* Ether */ |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 41 | #define CONFIG_SH_ETHER_USE_PORT 0 |
| 42 | #define CONFIG_SH_ETHER_PHY_ADDR 1 |
| 43 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 |
Yoshihiro Shimoda | 8667163 | 2011-10-11 18:11:03 +0900 | [diff] [blame] | 44 | #define CONFIG_BITBANGMII_MULTI |
Nobuhiro Iwamatsu | 32f900e | 2012-05-16 10:23:21 +0900 | [diff] [blame] | 45 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 46 | |
| 47 | #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 |
| 48 | #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) |
| 49 | #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI |
| 50 | #define SH7757LCR_ETHERNET_MAC_SIZE 17 |
| 51 | #define SH7757LCR_ETHERNET_NUM_CH 2 |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 52 | |
| 53 | /* Gigabit Ether */ |
| 54 | #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 |
| 55 | |
| 56 | /* SPI */ |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 57 | #define CONFIG_SH_SPI_BASE 0xfe002000 |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 58 | |
Yoshihiro Shimoda | 6ff2494 | 2012-03-05 20:11:12 +0000 | [diff] [blame] | 59 | /* MMCIF */ |
Yoshihiro Shimoda | 6ff2494 | 2012-03-05 20:11:12 +0000 | [diff] [blame] | 60 | #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 |
| 61 | #define CONFIG_SH_MMCIF_CLK 48000000 |
| 62 | |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 63 | /* SH7757 board */ |
| 64 | #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 |
| 65 | #define SH7757LCR_GRA_OFFSET 0x1f000000 |
| 66 | #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 |
| 67 | #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) |
| 68 | #define SH7757LCR_PCIEBRG_ADDR 0x00090000 |
| 69 | #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) |
| 70 | |
| 71 | /* ENV setting */ |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 72 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 73 | "netboot=bootp; bootm\0" |
| 74 | |
| 75 | /* Board Clock */ |
| 76 | #define CONFIG_SYS_CLK_FREQ 48000000 |
Nobuhiro Iwamatsu | e698449 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 77 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Yoshihiro Shimoda | a7d382c | 2011-02-02 10:05:36 +0900 | [diff] [blame] | 78 | #endif /* __SH7757LCR_H */ |