Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
Meenakshi Aggarwal | 751f7a7 | 2020-01-10 20:13:19 +0530 | [diff] [blame] | 3 | * Copyright 2018-2020 NXP |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __LX2_COMMON_H |
| 7 | #define __LX2_COMMON_H |
| 8 | |
| 9 | #include <asm/arch/stream_id_lsch3.h> |
| 10 | #include <asm/arch/config.h> |
| 11 | #include <asm/arch/soc.h> |
| 12 | |
| 13 | #define CONFIG_REMAKE_ELF |
| 14 | #define CONFIG_FSL_LAYERSCAPE |
| 15 | #define CONFIG_GICV3 |
| 16 | #define CONFIG_FSL_TZPC_BP147 |
| 17 | #define CONFIG_FSL_MEMAC |
| 18 | |
| 19 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE |
| 20 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 21 | |
| 22 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 23 | |
| 24 | /* DDR */ |
| 25 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
| 26 | #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ |
| 27 | #define CONFIG_VERY_BIG_RAM |
| 28 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
| 29 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
| 30 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL |
| 31 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 |
| 32 | #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL |
| 33 | #define CONFIG_DDR_SPD |
| 34 | #define CONFIG_DDR_ECC |
| 35 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 36 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 37 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 38 | #define SPD_EEPROM_ADDRESS1 0x51 |
| 39 | #define SPD_EEPROM_ADDRESS2 0x52 |
| 40 | #define SPD_EEPROM_ADDRESS3 0x53 |
| 41 | #define SPD_EEPROM_ADDRESS4 0x54 |
| 42 | #define SPD_EEPROM_ADDRESS5 0x55 |
| 43 | #define SPD_EEPROM_ADDRESS6 0x56 |
| 44 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 |
| 45 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ |
| 46 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 47 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
| 48 | #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ |
| 49 | #define CONFIG_SYS_MONITOR_LEN (936 * 1024) |
| 50 | |
| 51 | /* Miscellaneous configurable options */ |
| 52 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) |
| 53 | |
| 54 | /* SMP Definitinos */ |
Michael Walle | f056e0f | 2020-06-01 21:53:26 +0200 | [diff] [blame] | 55 | #define CPU_RELEASE_ADDR secondary_boot_addr |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 56 | |
| 57 | /* Generic Timer Definitions */ |
| 58 | /* |
| 59 | * This is not an accurate number. It is used in start.S. The frequency |
| 60 | * will be udpated later when get_bus_freq(0) is available. |
| 61 | */ |
| 62 | |
| 63 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
| 64 | |
| 65 | /* Size of malloc() pool */ |
| 66 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) |
| 67 | |
| 68 | /* Serial Port */ |
| 69 | #define CONFIG_PL01X_SERIAL |
| 70 | #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) |
| 71 | #define CONFIG_SYS_SERIAL0 0x21c0000 |
| 72 | #define CONFIG_SYS_SERIAL1 0x21d0000 |
| 73 | #define CONFIG_SYS_SERIAL2 0x21e0000 |
| 74 | #define CONFIG_SYS_SERIAL3 0x21f0000 |
| 75 | /*below might needs to be removed*/ |
| 76 | #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ |
| 77 | (void *)CONFIG_SYS_SERIAL1, \ |
| 78 | (void *)CONFIG_SYS_SERIAL2, \ |
| 79 | (void *)CONFIG_SYS_SERIAL3 } |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 80 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 81 | |
| 82 | /* MC firmware */ |
| 83 | #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 |
| 84 | #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 |
| 85 | #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 |
| 86 | #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 |
| 87 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
| 88 | |
| 89 | /* Define phy_reset function to boot the MC based on mcinitcmd. |
| 90 | * This happens late enough to properly fixup u-boot env MAC addresses. |
| 91 | */ |
| 92 | #define CONFIG_RESET_PHY_R |
| 93 | |
| 94 | /* |
| 95 | * Carve out a DDR region which will not be used by u-boot/Linux |
| 96 | * |
| 97 | * It will be used by MC and Debug Server. The MC region must be |
| 98 | * 512MB aligned, so the min size to hide is 512MB. |
| 99 | */ |
| 100 | #ifdef CONFIG_FSL_MC_ENET |
Meenakshi Aggarwal | 67f195c | 2019-02-27 14:41:02 +0530 | [diff] [blame] | 101 | #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 102 | #endif |
| 103 | |
| 104 | /* I2C bus multiplexer */ |
| 105 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ |
| 106 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 107 | |
| 108 | /* RTC */ |
| 109 | #define RTC |
| 110 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ |
| 111 | |
| 112 | /* EEPROM */ |
| 113 | #define CONFIG_ID_EEPROM |
| 114 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 115 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 116 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 117 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 118 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 119 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 120 | |
| 121 | /* Qixis */ |
| 122 | #define CONFIG_FSL_QIXIS |
| 123 | #define CONFIG_QIXIS_I2C_ACCESS |
| 124 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
| 125 | |
| 126 | /* PCI */ |
| 127 | #ifdef CONFIG_PCI |
| 128 | #define CONFIG_SYS_PCI_64BIT |
| 129 | #define CONFIG_PCI_SCAN_SHOW |
| 130 | #endif |
| 131 | |
| 132 | /* MMC */ |
| 133 | #ifdef CONFIG_MMC |
| 134 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| 135 | #endif |
| 136 | |
| 137 | /* SATA */ |
| 138 | |
| 139 | #ifdef CONFIG_SCSI |
| 140 | #define CONFIG_SCSI_AHCI_PLAT |
| 141 | #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 |
| 142 | #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 |
| 143 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
| 144 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 145 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| 146 | CONFIG_SYS_SCSI_MAX_LUN) |
| 147 | #endif |
| 148 | |
| 149 | /* USB */ |
| 150 | #ifdef CONFIG_USB |
| 151 | #define CONFIG_HAS_FSL_XHCI_USB |
| 152 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 153 | #endif |
| 154 | |
| 155 | /* FlexSPI */ |
| 156 | #ifdef CONFIG_NXP_FSPI |
| 157 | #define NXP_FSPI_FLASH_SIZE SZ_64M |
| 158 | #define NXP_FSPI_FLASH_NUM 1 |
| 159 | #endif |
| 160 | |
| 161 | #ifndef __ASSEMBLY__ |
| 162 | unsigned long get_board_sys_clk(void); |
| 163 | unsigned long get_board_ddr_clk(void); |
| 164 | #endif |
| 165 | |
| 166 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 167 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
| 168 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) |
| 169 | |
| 170 | #define CONFIG_HWCONFIG |
| 171 | #define HWCONFIG_BUFFER_SIZE 128 |
| 172 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 173 | /* Monitor Command Prompt */ |
| 174 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 175 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 176 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 177 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 178 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 179 | |
| 180 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 181 | |
| 182 | /* Initial environment variables */ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 183 | #define XSPI_MC_INIT_CMD \ |
| 184 | "sf probe 0:0 && " \ |
| 185 | "sf read 0x80640000 0x640000 0x80000 && " \ |
| 186 | "env exists secureboot && " \ |
| 187 | "esbc_validate 0x80640000 && " \ |
| 188 | "esbc_validate 0x80680000; " \ |
| 189 | "sf read 0x80a00000 0xa00000 0x300000 && " \ |
| 190 | "sf read 0x80e00000 0xe00000 0x100000; " \ |
| 191 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 192 | |
| 193 | #define SD_MC_INIT_CMD \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 194 | "mmc read 0x80a00000 0x5000 0x1200;" \ |
| 195 | "mmc read 0x80e00000 0x7000 0x800;" \ |
Udit Agarwal | f34581e | 2018-12-14 04:43:32 +0000 | [diff] [blame] | 196 | "env exists secureboot && " \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 197 | "mmc read 0x80640000 0x3200 0x20 && " \ |
| 198 | "mmc read 0x80680000 0x3400 0x20 && " \ |
| 199 | "esbc_validate 0x80640000 && " \ |
| 200 | "esbc_validate 0x80680000 ;" \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 201 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 202 | |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 203 | #define SD2_MC_INIT_CMD \ |
| 204 | "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \ |
| 205 | "mmc read 0x80e00000 0x7000 0x800;" \ |
| 206 | "env exists secureboot && " \ |
| 207 | "mmc read 0x80640000 0x3200 0x20 && " \ |
| 208 | "mmc read 0x80680000 0x3400 0x20 && " \ |
| 209 | "esbc_validate 0x80640000 && " \ |
| 210 | "esbc_validate 0x80680000 ;" \ |
| 211 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
| 212 | |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 213 | #define EXTRA_ENV_SETTINGS \ |
| 214 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 215 | "ramdisk_addr=0x800000\0" \ |
| 216 | "ramdisk_size=0x2000000\0" \ |
| 217 | "fdt_high=0xa0000000\0" \ |
| 218 | "initrd_high=0xffffffffffffffff\0" \ |
| 219 | "fdt_addr=0x64f00000\0" \ |
| 220 | "kernel_start=0x1000000\0" \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 221 | "kernelheader_start=0x600000\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 222 | "scriptaddr=0x80000000\0" \ |
| 223 | "scripthdraddr=0x80080000\0" \ |
| 224 | "fdtheader_addr_r=0x80100000\0" \ |
| 225 | "kernelheader_addr_r=0x80200000\0" \ |
| 226 | "kernel_addr_r=0x81000000\0" \ |
| 227 | "kernelheader_size=0x40000\0" \ |
| 228 | "fdt_addr_r=0x90000000\0" \ |
| 229 | "load_addr=0xa0000000\0" \ |
| 230 | "kernel_size=0x2800000\0" \ |
| 231 | "kernel_addr_sd=0x8000\0" \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 232 | "kernelhdr_addr_sd=0x3000\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 233 | "kernel_size_sd=0x1d000\0" \ |
Udit Agarwal | 11e1a57 | 2019-11-20 08:49:06 +0000 | [diff] [blame] | 234 | "kernelhdr_size_sd=0x20\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 235 | "console=ttyAMA0,38400n8\0" \ |
| 236 | BOOTENV \ |
| 237 | "mcmemsize=0x70000000\0" \ |
| 238 | XSPI_MC_INIT_CMD \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 239 | "scan_dev_for_boot_part=" \ |
| 240 | "part list ${devtype} ${devnum} devplist; " \ |
| 241 | "env exists devplist || setenv devplist 1; " \ |
| 242 | "for distro_bootpart in ${devplist}; do " \ |
| 243 | "if fstype ${devtype} " \ |
| 244 | "${devnum}:${distro_bootpart} " \ |
| 245 | "bootfstype; then " \ |
| 246 | "run scan_dev_for_boot; " \ |
| 247 | "fi; " \ |
| 248 | "done\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 249 | "boot_a_script=" \ |
| 250 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 251 | "${scriptaddr} ${prefix}${script}; " \ |
| 252 | "env exists secureboot && load ${devtype} " \ |
| 253 | "${devnum}:${distro_bootpart} " \ |
| 254 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ |
| 255 | "&& esbc_validate ${scripthdraddr};" \ |
| 256 | "source ${scriptaddr}\0" |
| 257 | |
| 258 | #define XSPI_NOR_BOOTCOMMAND \ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 259 | "sf probe 0:0; " \ |
| 260 | "sf read 0x806c0000 0x6c0000 0x40000; " \ |
| 261 | "env exists mcinitcmd && env exists secureboot" \ |
| 262 | " && esbc_validate 0x806c0000; " \ |
| 263 | "sf read 0x80d00000 0xd00000 0x100000; " \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 264 | "env exists mcinitcmd && " \ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 265 | "fsl_mc lazyapply dpl 0x80d00000; " \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 266 | "run distro_bootcmd;run xspi_bootcmd; " \ |
| 267 | "env exists secureboot && esbc_halt;" |
| 268 | |
| 269 | #define SD_BOOTCOMMAND \ |
| 270 | "env exists mcinitcmd && mmcinfo; " \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 271 | "mmc read 0x80d00000 0x6800 0x800; " \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 272 | "env exists mcinitcmd && env exists secureboot " \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 273 | " && mmc read 0x806C0000 0x3600 0x20 " \ |
| 274 | "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 275 | "&& fsl_mc lazyapply dpl 0x80d00000;" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 276 | "run distro_bootcmd;run sd_bootcmd;" \ |
| 277 | "env exists secureboot && esbc_halt;" |
| 278 | |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 279 | #define SD2_BOOTCOMMAND \ |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 280 | "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 281 | "mmc read 0x80d00000 0x6800 0x800; " \ |
| 282 | "env exists mcinitcmd && env exists secureboot " \ |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 283 | " && mmc read 0x806C0000 0x3600 0x20 " \ |
| 284 | "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 285 | "&& fsl_mc lazyapply dpl 0x80d00000;" \ |
| 286 | "run distro_bootcmd;run sd2_bootcmd;" \ |
| 287 | "env exists secureboot && esbc_halt;" |
| 288 | |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 289 | #define BOOT_TARGET_DEVICES(func) \ |
| 290 | func(USB, usb, 0) \ |
| 291 | func(MMC, mmc, 0) \ |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 292 | func(MMC, mmc, 1) \ |
Meenakshi Aggarwal | 2622464 | 2020-03-11 20:51:47 +0530 | [diff] [blame] | 293 | func(SCSI, scsi, 0) \ |
| 294 | func(DHCP, dhcp, na) |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 295 | #include <config_distro_bootcmd.h> |
| 296 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 297 | #endif /* __LX2_COMMON_H */ |