blob: cf4d60ad60327c6fef8de2e27850eaeb33e39be1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Feng Li39e112d2016-11-03 14:15:17 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Biwen Lid15aa9f2019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Feng Li39e112d2016-11-03 14:15:17 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Feng Li39e112d2016-11-03 14:15:17 +080010#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11
12#define CONFIG_SYS_FSL_CLK
13
Feng Li39e112d2016-11-03 14:15:17 +080014/*
15 * Size of malloc() pool
16 */
17#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
18
19#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
20#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
21
Feng Li39e112d2016-11-03 14:15:17 +080022#define CONFIG_SYS_CLK_FREQ 100000000
23#define CONFIG_DDR_CLK_FREQ 100000000
24
25/*
26 * DDR: 800 MHz ( 1600 MT/s data rate )
27 */
28
29#define DDR_SDRAM_CFG 0x470c0008
30#define DDR_CS0_BNDS 0x008000bf
31#define DDR_CS0_CONFIG 0x80014302
32#define DDR_TIMING_CFG_0 0x50550004
33#define DDR_TIMING_CFG_1 0xbcb38c56
34#define DDR_TIMING_CFG_2 0x0040d120
35#define DDR_TIMING_CFG_3 0x010e1000
36#define DDR_TIMING_CFG_4 0x00000001
37#define DDR_TIMING_CFG_5 0x03401400
38#define DDR_SDRAM_CFG_2 0x00401010
39#define DDR_SDRAM_MODE 0x00061c60
40#define DDR_SDRAM_MODE_2 0x00180000
41#define DDR_SDRAM_INTERVAL 0x18600618
42#define DDR_DDR_WRLVL_CNTL 0x8655f605
43#define DDR_DDR_WRLVL_CNTL_2 0x05060607
44#define DDR_DDR_WRLVL_CNTL_3 0x05050505
45#define DDR_DDR_CDR1 0x80040000
46#define DDR_DDR_CDR2 0x00000001
47#define DDR_SDRAM_CLK_CNTL 0x02000000
48#define DDR_DDR_ZQ_CNTL 0x89080600
49#define DDR_CS0_CONFIG_2 0
50#define DDR_SDRAM_CFG_MEM_EN 0x80000000
51#define SDRAM_CFG2_D_INIT 0x00000010
52#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
53#define SDRAM_CFG2_FRC_SR 0x80000000
54#define SDRAM_CFG_BI 0x00000001
55
56#ifdef CONFIG_RAMBOOT_PBL
57#define CONFIG_SYS_FSL_PBL_PBI \
58 board/freescale/ls1021aiot/ls102xa_pbi.cfg
59#endif
60
61#ifdef CONFIG_SD_BOOT
62#define CONFIG_SYS_FSL_PBL_RCW \
63 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
Feng Li39e112d2016-11-03 14:15:17 +080064#define CONFIG_SPL_LIBCOMMON_SUPPORT
65#define CONFIG_SPL_LIBGENERIC_SUPPORT
66#define CONFIG_SPL_ENV_SUPPORT
67#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
68#define CONFIG_SPL_I2C_SUPPORT
69#define CONFIG_SPL_WATCHDOG_SUPPORT
Feng Li39e112d2016-11-03 14:15:17 +080070#define CONFIG_SPL_MMC_SUPPORT
71#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
Feng Li39e112d2016-11-03 14:15:17 +080072
Feng Li39e112d2016-11-03 14:15:17 +080073#define CONFIG_SPL_MAX_SIZE 0x1a000
74#define CONFIG_SPL_STACK 0x1001d000
75#define CONFIG_SPL_PAD_TO 0x1c000
Feng Li39e112d2016-11-03 14:15:17 +080076
77#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
78 CONFIG_SYS_MONITOR_LEN)
79#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
80#define CONFIG_SPL_BSS_START_ADDR 0x80100000
81#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
82#define CONFIG_SYS_MONITOR_LEN 0x80000
Feng Li39e112d2016-11-03 14:15:17 +080083#endif
84
Feng Li39e112d2016-11-03 14:15:17 +080085#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
87
Alison Wangd6be97b2019-03-06 14:49:14 +080088#define CONFIG_CHIP_SELECTS_PER_CTRL 4
89
Feng Li39e112d2016-11-03 14:15:17 +080090/*
91 * Serial Port
92 */
Feng Li39e112d2016-11-03 14:15:17 +080093#define CONFIG_SYS_NS16550_SERIAL
94#define CONFIG_SYS_NS16550_REG_SIZE 1
95#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Feng Li39e112d2016-11-03 14:15:17 +080096
97/*
98 * I2C
99 */
Biwen Lid15aa9f2019-12-31 15:33:44 +0800100
101#ifndef CONFIG_DM_I2C
Feng Li39e112d2016-11-03 14:15:17 +0800102#define CONFIG_SYS_I2C
Biwen Lid15aa9f2019-12-31 15:33:44 +0800103#else
104#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
105#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
106#endif
Feng Li39e112d2016-11-03 14:15:17 +0800107#define CONFIG_SYS_I2C_MXC
108#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
109#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
110#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
111
112/* EEPROM */
113#define CONFIG_ID_EEPROM
114#define CONFIG_SYS_I2C_EEPROM_NXID
115#define CONFIG_SYS_EEPROM_BUS_NUM 0
116#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
117#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
118
119/*
120 * MMC
121 */
Feng Li39e112d2016-11-03 14:15:17 +0800122
123/* SATA */
Feng Li39e112d2016-11-03 14:15:17 +0800124#define CONFIG_SCSI_AHCI_PLAT
125#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
126#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
127#endif
128#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
129 PCI_DEVICE_ID_FREESCALE_AHCI}
130
131#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
132#define CONFIG_SYS_SCSI_MAX_LUN 1
133#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
134 CONFIG_SYS_SCSI_MAX_LUN)
135
Feng Li39e112d2016-11-03 14:15:17 +0800136/* SPI */
137#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
138#define CONFIG_SPI_FLASH_SPANSION
Feng Li39e112d2016-11-03 14:15:17 +0800139#endif
140
Feng Li39e112d2016-11-03 14:15:17 +0800141/*
142 * eTSEC
143 */
Feng Li39e112d2016-11-03 14:15:17 +0800144
145#ifdef CONFIG_TSEC_ENET
Feng Li39e112d2016-11-03 14:15:17 +0800146#define CONFIG_MII_DEFAULT_TSEC 1
147#define CONFIG_TSEC1 1
148#define CONFIG_TSEC1_NAME "eTSEC1"
149#define CONFIG_TSEC2 1
150#define CONFIG_TSEC2_NAME "eTSEC2"
151
152#define TSEC1_PHY_ADDR 1
153#define TSEC2_PHY_ADDR 3
154
155#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
156#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
157
158#define TSEC1_PHYIDX 0
159#define TSEC2_PHYIDX 0
160
161#define CONFIG_ETHPRIME "eTSEC2"
162
Feng Li39e112d2016-11-03 14:15:17 +0800163#define CONFIG_HAS_ETH0
164#define CONFIG_HAS_ETH1
165#define CONFIG_HAS_ETH2
166#endif
167
168/* PCIe */
Feng Li39e112d2016-11-03 14:15:17 +0800169#define CONFIG_PCIE1 /* PCIE controler 1 */
170#define CONFIG_PCIE2 /* PCIE controler 2 */
171
Feng Li39e112d2016-11-03 14:15:17 +0800172#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
173
Feng Li39e112d2016-11-03 14:15:17 +0800174#ifdef CONFIG_PCI
Feng Li39e112d2016-11-03 14:15:17 +0800175#define CONFIG_PCI_SCAN_SHOW
Feng Li39e112d2016-11-03 14:15:17 +0800176#endif
177
Feng Li39e112d2016-11-03 14:15:17 +0800178#define CONFIG_CMDLINE_TAG
Feng Li39e112d2016-11-03 14:15:17 +0800179
Feng Li39e112d2016-11-03 14:15:17 +0800180#define CONFIG_PEN_ADDR_BIG_ENDIAN
181#define CONFIG_LAYERSCAPE_NS_ACCESS
182#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywara70c78932017-02-16 01:20:19 +0000183#define COUNTER_FREQUENCY 12500000
Feng Li39e112d2016-11-03 14:15:17 +0800184
185#define CONFIG_HWCONFIG
186#define HWCONFIG_BUFFER_SIZE 256
187
188#define CONFIG_FSL_DEVICE_DISABLE
189
190#define CONFIG_EXTRA_ENV_SETTINGS \
191 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang71477062020-02-03 15:25:19 +0800192"initrd_high=0xffffffff\0"
Feng Li39e112d2016-11-03 14:15:17 +0800193
194/*
195 * Miscellaneous configurable options
196 */
Alison Wang71477062020-02-03 15:25:19 +0800197#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
198
Feng Li39e112d2016-11-03 14:15:17 +0800199#define CONFIG_SYS_LOAD_ADDR 0x82000000
200
201#define CONFIG_LS102XA_STREAM_ID
202
Feng Li39e112d2016-11-03 14:15:17 +0800203#define CONFIG_SYS_INIT_SP_OFFSET \
204 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
205#define CONFIG_SYS_INIT_SP_ADDR \
206 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
207
208#ifdef CONFIG_SPL_BUILD
209#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
210#else
211/* start of monitor */
212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
213#endif
214
215#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
216
Feng Li39e112d2016-11-03 14:15:17 +0800217#define CONFIG_OF_BOARD_SETUP
218#define CONFIG_OF_STDOUT_VIA_ALIAS
Feng Li39e112d2016-11-03 14:15:17 +0800219
Feng Li39e112d2016-11-03 14:15:17 +0800220#include <asm/fsl_secure_boot.h>
221
222#endif