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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00002/*
3 * (C) Copyright 2001
4 * Denis Peter MPL AG Switzerland. d.peter@mpl.ch
wdenkaffae2b2002-08-17 09:36:01 +00005 */
6
7/*
8 * Date & Time support for the MC146818 (PIXX4) RTC
9 */
10
wdenkaffae2b2002-08-17 09:36:01 +000011#include <common.h>
12#include <command.h>
Bin Meng5c8c6b52015-06-23 12:18:41 +080013#include <dm.h>
wdenkaffae2b2002-08-17 09:36:01 +000014#include <rtc.h>
15
Simon Glass43d7c792016-09-25 21:33:11 -060016#if defined(CONFIG_X86) || defined(CONFIG_MALTA)
Graeme Russb87c30f2011-02-12 15:11:43 +110017#include <asm/io.h>
18#define in8(p) inb(p)
19#define out8(p, v) outb(v, p)
20#endif
21
Michal Simekc3e6c552008-07-14 19:45:37 +020022#if defined(CONFIG_CMD_DATE)
wdenkaffae2b2002-08-17 09:36:01 +000023
Simon Glass538059d2014-11-14 18:18:26 -070024/* Set this to 1 to clear the CMOS RAM */
Bin Meng5c8c6b52015-06-23 12:18:41 +080025#define CLEAR_CMOS 0
Simon Glass538059d2014-11-14 18:18:26 -070026
Bin Meng5c8c6b52015-06-23 12:18:41 +080027#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
Wolfgang Denka1be4762008-05-20 16:00:29 +020028#define RTC_SECONDS 0x00
29#define RTC_SECONDS_ALARM 0x01
30#define RTC_MINUTES 0x02
31#define RTC_MINUTES_ALARM 0x03
32#define RTC_HOURS 0x04
33#define RTC_HOURS_ALARM 0x05
34#define RTC_DAY_OF_WEEK 0x06
35#define RTC_DATE_OF_MONTH 0x07
36#define RTC_MONTH 0x08
37#define RTC_YEAR 0x09
Bin Meng5c8c6b52015-06-23 12:18:41 +080038#define RTC_CONFIG_A 0x0a
39#define RTC_CONFIG_B 0x0b
40#define RTC_CONFIG_C 0x0c
41#define RTC_CONFIG_D 0x0d
Simon Glass538059d2014-11-14 18:18:26 -070042#define RTC_REG_SIZE 0x80
43
44#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5)
45#define RTC_CONFIG_A_RATE_1024HZ 6
wdenkaffae2b2002-08-17 09:36:01 +000046
Simon Glass538059d2014-11-14 18:18:26 -070047#define RTC_CONFIG_B_24H (1 << 1)
48
49#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80
wdenkaffae2b2002-08-17 09:36:01 +000050
Bin Meng5c8c6b52015-06-23 12:18:41 +080051static int mc146818_read8(int reg)
wdenkaffae2b2002-08-17 09:36:01 +000052{
Simon Glassb4ae6002015-01-19 22:16:10 -070053#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
Simon Glass538059d2014-11-14 18:18:26 -070054 return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
Simon Glassb4ae6002015-01-19 22:16:10 -070055#else
56 int ofs = 0;
57
58 if (reg >= 128) {
59 ofs = 2;
60 reg -= 128;
61 }
62 out8(RTC_PORT_MC146818 + ofs, reg);
63
64 return in8(RTC_PORT_MC146818 + ofs + 1);
65#endif
wdenkaffae2b2002-08-17 09:36:01 +000066}
67
Bin Meng5c8c6b52015-06-23 12:18:41 +080068static void mc146818_write8(int reg, uchar val)
wdenkaffae2b2002-08-17 09:36:01 +000069{
Simon Glassb4ae6002015-01-19 22:16:10 -070070#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
Simon Glass538059d2014-11-14 18:18:26 -070071 out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
wdenkaffae2b2002-08-17 09:36:01 +000072#else
Simon Glassb4ae6002015-01-19 22:16:10 -070073 int ofs = 0;
74
75 if (reg >= 128) {
76 ofs = 2;
77 reg -= 128;
78 }
79 out8(RTC_PORT_MC146818 + ofs, reg);
80 out8(RTC_PORT_MC146818 + ofs + 1, val);
81#endif
82}
83
Bin Meng5c8c6b52015-06-23 12:18:41 +080084static int mc146818_get(struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000085{
Bin Meng5c8c6b52015-06-23 12:18:41 +080086 uchar sec, min, hour, mday, wday, mon, year;
Simon Glassb4ae6002015-01-19 22:16:10 -070087
Bin Meng5c8c6b52015-06-23 12:18:41 +080088 /* here check if rtc can be accessed */
89 while ((mc146818_read8(RTC_CONFIG_A) & 0x80) == 0x80)
90 ;
Simon Glassb4ae6002015-01-19 22:16:10 -070091
Bin Meng5c8c6b52015-06-23 12:18:41 +080092 sec = mc146818_read8(RTC_SECONDS);
93 min = mc146818_read8(RTC_MINUTES);
94 hour = mc146818_read8(RTC_HOURS);
95 mday = mc146818_read8(RTC_DATE_OF_MONTH);
96 wday = mc146818_read8(RTC_DAY_OF_WEEK);
97 mon = mc146818_read8(RTC_MONTH);
98 year = mc146818_read8(RTC_YEAR);
99#ifdef RTC_DEBUG
100 printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x hr: %02x min: %02x sec: %02x\n",
101 year, mon, mday, wday, hour, min, sec);
Bin Mengb49eb3f2017-10-17 08:19:33 -0700102 printf("Alarms: mday: %02x hour: %02x min: %02x sec: %02x\n",
Bin Meng5c8c6b52015-06-23 12:18:41 +0800103 mc146818_read8(RTC_CONFIG_D) & 0x3f,
104 mc146818_read8(RTC_HOURS_ALARM),
105 mc146818_read8(RTC_MINUTES_ALARM),
106 mc146818_read8(RTC_SECONDS_ALARM));
107#endif
108 tmp->tm_sec = bcd2bin(sec & 0x7f);
109 tmp->tm_min = bcd2bin(min & 0x7f);
110 tmp->tm_hour = bcd2bin(hour & 0x3f);
111 tmp->tm_mday = bcd2bin(mday & 0x3f);
112 tmp->tm_mon = bcd2bin(mon & 0x1f);
113 tmp->tm_year = bcd2bin(year);
114 tmp->tm_wday = bcd2bin(wday & 0x07);
115
116 if (tmp->tm_year < 70)
117 tmp->tm_year += 2000;
118 else
119 tmp->tm_year += 1900;
120
121 tmp->tm_yday = 0;
122 tmp->tm_isdst = 0;
123#ifdef RTC_DEBUG
124 printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
125 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
126 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
127#endif
128
129 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000130}
131
Bin Meng5c8c6b52015-06-23 12:18:41 +0800132static int mc146818_set(struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000133{
Bin Meng5c8c6b52015-06-23 12:18:41 +0800134#ifdef RTC_DEBUG
135 printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
136 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
137 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
138#endif
139 /* Disable the RTC to update the regs */
140 mc146818_write8(RTC_CONFIG_B, 0x82);
Simon Glassb4ae6002015-01-19 22:16:10 -0700141
Bin Meng5c8c6b52015-06-23 12:18:41 +0800142 mc146818_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100));
143 mc146818_write8(RTC_MONTH, bin2bcd(tmp->tm_mon));
144 mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
145 mc146818_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
146 mc146818_write8(RTC_HOURS, bin2bcd(tmp->tm_hour));
147 mc146818_write8(RTC_MINUTES, bin2bcd(tmp->tm_min));
148 mc146818_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec));
149
150 /* Enable the RTC to update the regs */
151 mc146818_write8(RTC_CONFIG_B, 0x02);
152
153 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000154}
wdenkaffae2b2002-08-17 09:36:01 +0000155
Bin Meng5c8c6b52015-06-23 12:18:41 +0800156static void mc146818_reset(void)
157{
158 /* Disable the RTC to update the regs */
159 mc146818_write8(RTC_CONFIG_B, 0x82);
160
161 /* Normal OP */
162 mc146818_write8(RTC_CONFIG_A, 0x20);
163 mc146818_write8(RTC_CONFIG_B, 0x00);
164 mc146818_write8(RTC_CONFIG_B, 0x00);
165
166 /* Enable the RTC to update the regs */
167 mc146818_write8(RTC_CONFIG_B, 0x02);
168}
169
170static void mc146818_init(void)
Simon Glass538059d2014-11-14 18:18:26 -0700171{
172#if CLEAR_CMOS
173 int i;
174
Simon Glassb4ae6002015-01-19 22:16:10 -0700175 rtc_write8(RTC_SECONDS_ALARM, 0);
176 rtc_write8(RTC_MINUTES_ALARM, 0);
177 rtc_write8(RTC_HOURS_ALARM, 0);
Simon Glass538059d2014-11-14 18:18:26 -0700178 for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++)
Simon Glassb4ae6002015-01-19 22:16:10 -0700179 rtc_write8(i, 0);
Simon Glass538059d2014-11-14 18:18:26 -0700180 printf("RTC: zeroing CMOS RAM\n");
181#endif
182
183 /* Setup the real time clock */
Bin Meng5c8c6b52015-06-23 12:18:41 +0800184 mc146818_write8(RTC_CONFIG_B, RTC_CONFIG_B_24H);
Simon Glass538059d2014-11-14 18:18:26 -0700185 /* Setup the frequency it operates at */
Bin Meng5c8c6b52015-06-23 12:18:41 +0800186 mc146818_write8(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
187 RTC_CONFIG_A_RATE_1024HZ);
Simon Glass538059d2014-11-14 18:18:26 -0700188 /* Ensure all reserved bits are 0 in register D */
Bin Meng5c8c6b52015-06-23 12:18:41 +0800189 mc146818_write8(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
Simon Glass538059d2014-11-14 18:18:26 -0700190
191 /* Clear any pending interrupts */
Bin Meng5c8c6b52015-06-23 12:18:41 +0800192 mc146818_read8(RTC_CONFIG_C);
Simon Glass538059d2014-11-14 18:18:26 -0700193}
Simon Glassbc932072015-10-18 15:55:29 -0600194#endif /* CONFIG_CMD_DATE */
Bin Meng5c8c6b52015-06-23 12:18:41 +0800195
196#ifdef CONFIG_DM_RTC
197
198static int rtc_mc146818_get(struct udevice *dev, struct rtc_time *time)
199{
200 return mc146818_get(time);
201}
202
203static int rtc_mc146818_set(struct udevice *dev, const struct rtc_time *time)
204{
205 return mc146818_set((struct rtc_time *)time);
206}
207
208static int rtc_mc146818_reset(struct udevice *dev)
209{
210 mc146818_reset();
211
212 return 0;
213}
214
215static int rtc_mc146818_read8(struct udevice *dev, unsigned int reg)
216{
217 return mc146818_read8(reg);
218}
219
220static int rtc_mc146818_write8(struct udevice *dev, unsigned int reg, int val)
221{
222 mc146818_write8(reg, val);
223
224 return 0;
225}
226
Simon Glassa10166f2015-10-18 15:55:30 -0600227static int rtc_mc146818_probe(struct udevice *dev)
Bin Meng5c8c6b52015-06-23 12:18:41 +0800228{
229 mc146818_init();
230
231 return 0;
232}
233
234static const struct rtc_ops rtc_mc146818_ops = {
235 .get = rtc_mc146818_get,
236 .set = rtc_mc146818_set,
237 .reset = rtc_mc146818_reset,
238 .read8 = rtc_mc146818_read8,
239 .write8 = rtc_mc146818_write8,
240};
241
242static const struct udevice_id rtc_mc146818_ids[] = {
243 { .compatible = "motorola,mc146818" },
244 { }
245};
246
247U_BOOT_DRIVER(rtc_mc146818) = {
248 .name = "rtc_mc146818",
249 .id = UCLASS_RTC,
250 .of_match = rtc_mc146818_ids,
Simon Glassa10166f2015-10-18 15:55:30 -0600251 .probe = rtc_mc146818_probe,
Bin Meng5c8c6b52015-06-23 12:18:41 +0800252 .ops = &rtc_mc146818_ops,
253};
254
255#else /* !CONFIG_DM_RTC */
256
257int rtc_get(struct rtc_time *tmp)
258{
259 return mc146818_get(tmp);
260}
261
262int rtc_set(struct rtc_time *tmp)
263{
264 return mc146818_set(tmp);
265}
266
267void rtc_reset(void)
268{
269 mc146818_reset();
270}
271
272int rtc_read8(int reg)
273{
274 return mc146818_read8(reg);
275}
276
277void rtc_write8(int reg, uchar val)
278{
279 mc146818_write8(reg, val);
280}
281
282u32 rtc_read32(int reg)
283{
284 u32 value = 0;
285 int i;
286
287 for (i = 0; i < sizeof(value); i++)
288 value |= rtc_read8(reg + i) << (i << 3);
289
290 return value;
291}
292
293void rtc_write32(int reg, u32 value)
294{
295 int i;
296
297 for (i = 0; i < sizeof(value); i++)
298 rtc_write8(reg + i, (value >> (i << 3)) & 0xff);
299}
300
301void rtc_init(void)
302{
303 mc146818_init();
304}
305
306#endif /* CONFIG_DM_RTC */