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git01.mediatek.com / filogic / uboot / 9c5970c73ace6f695c0c632e89291fd7df80d136 / . / configs / theadorable_debug_defconfig
blob: 34b740c6f2d1e4a3bb5533b6696593765f46e125 [file] [log] [blame]
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]3CONFIG_ARCH_MVEBU=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x00800000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]5CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]6CONFIG_SPL_LIBGENERIC_SUPPORT=y
Masahiro Yamada75794f92016-09-19 21:40:26 +0900[diff] [blame]7CONFIG_SYS_MALLOC_F_LEN=0x2000
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]8CONFIG_TARGET_THEADORABLE=y
Simon Glasse076d6f2016-09-12 23:18:56 -0600[diff] [blame]9CONFIG_SPL_SERIAL_SUPPORT=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]10CONFIG_NR_DRAM_BANKS=2
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_SPL=y
12CONFIG_DEBUG_UART_BASE=0xd0012000
13CONFIG_DEBUG_UART_CLOCK=250000000
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]14CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]15CONFIG_SPL_SPI_SUPPORT=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]16CONFIG_DEBUG_UART=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]17CONFIG_SPL_TEXT_BASE=0x40004030
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]18# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]19CONFIG_FIT=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]20CONFIG_BOOTDELAY=3
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]21CONFIG_USE_PREBOOT=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]22# CONFIG_CONSOLE_MUX is not set
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]23CONFIG_SYS_CONSOLE_INFO_QUIET=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]24# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]25CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]26CONFIG_SPL_I2C_SUPPORT=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]27CONFIG_SPL_SPI_LOAD=y
Hannes Schmelzer38df9972019-08-22 15:41:46 +0200[diff] [blame]28CONFIG_SYS_SPI_U_BOOT_OFFS=0x1a000
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]29CONFIG_HUSH_PARSER=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]30CONFIG_CMD_BOOTZ=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]31# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]32CONFIG_CMD_GPIO=y
33CONFIG_CMD_I2C=y
34CONFIG_CMD_PCI=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]35CONFIG_CMD_SF=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]36CONFIG_CMD_SPI=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]37CONFIG_CMD_USB=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]38CONFIG_CMD_DHCP=y
Tom Rinie8f8d672018-04-17 09:22:31 -0400[diff] [blame]39CONFIG_CMD_TFTPPUT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]40CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]41CONFIG_CMD_PING=y
Simon Glassb575bfc2017-04-26 22:27:55 -0600[diff] [blame]42CONFIG_CMD_BMP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]43CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]44CONFIG_CMD_TIME=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]45CONFIG_CMD_EXT2=y
46CONFIG_CMD_EXT4=y
47CONFIG_CMD_FAT=y
48CONFIG_CMD_FS_GENERIC=y
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]49CONFIG_EFI_PARTITION=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]50# CONFIG_PARTITION_UUIDS is not set
51# CONFIG_SPL_PARTITION_UUIDS is not set
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]52CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
Patrick Delaunayf8e932e2019-02-27 15:20:38 +0100[diff] [blame]53CONFIG_USE_ENV_SPI_MAX_HZ=y
54CONFIG_ENV_SPI_MAX_HZ=50000000
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]55CONFIG_NET_RANDOM_ETHADDR=y
56CONFIG_SPL_OF_TRANSLATE=y
Tuomas Tynkkynen9f1caca2017-12-08 15:36:16 +0200[diff] [blame]57CONFIG_SATA_MV=y
Stefan Roeseff396802019-03-11 13:29:21 +0100[diff] [blame]58CONFIG_BLK=y
Lukasz Majewski6dd8c902018-02-09 23:50:57 +0100[diff] [blame]59CONFIG_BOOTCOUNT_LIMIT=y
Alex Kiernan2a694292018-02-16 15:50:42 +0000[diff] [blame]60CONFIG_BOOTCOUNT_RAM=y
Tien Fong Chee647c5f32017-07-26 13:05:39 +0800[diff] [blame]61CONFIG_FPGA_ALTERA=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]62CONFIG_DM_GPIO=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]63# CONFIG_MMC is not set
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]64CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]65CONFIG_SF_DEFAULT_SPEED=27777777
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]66CONFIG_SPI_FLASH_MACRONIX=y
67CONFIG_SPI_FLASH_STMICRO=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]68CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]69CONFIG_PHY_GIGE=y
Chris Packham919041c2017-08-21 20:17:03 +1200[diff] [blame]70CONFIG_MVNETA=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]71CONFIG_MII=y
Tom Rinif48e0252016-10-26 17:15:37 -0400[diff] [blame]72CONFIG_PCI=y
Stefan Roese3179ec62019-01-25 11:52:43 +0100[diff] [blame]73CONFIG_DM_PCI_COMPAT=y
74CONFIG_PCI_MVEBU=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]75CONFIG_DEBUG_UART_SHIFT=2
76CONFIG_SYS_NS16550=y
Tuomas Tynkkynen13b5cb82018-02-07 02:42:22 +0200[diff] [blame]77CONFIG_KIRKWOOD_SPI=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]78CONFIG_USB=y
79CONFIG_DM_USB=y
80CONFIG_USB_EHCI_HCD=y
81CONFIG_USB_STORAGE=y
Stefan Roeseee4f68b2019-01-30 08:54:11 +0100[diff] [blame]82CONFIG_DM_VIDEO=y
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]83CONFIG_VIDEO_MVEBU=y