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git01.mediatek.com / filogic / uboot / 9c4197cdd4264699b2381209cf6ab0f5eb60030d / . / arch / arm / mach-rockchip / rv1126 / Kconfig
blob: 7382c5599661f28f6d68fd22fb4904d529388e13 [file] [log] [blame]
Jagan Teki249a2382022-12-14 23:21:05 +0530[diff] [blame]1if ROCKCHIP_RV1126
2
Jagan Teki1db421e2022-12-14 23:21:11 +0530[diff] [blame]3config TARGET_RV1126_NEU2
4 bool "Edgeble Neural Compute Module 2(Neu2) SoM"
5 help
6 Neu2:
7 Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
8 based on Rockchip RV1126 from Edgeble AI.
9 Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC.
10 Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC.
11
12 Neu2-IO:
13 Neural Compute Module 2(Neu2) IO board is an industrial form factor
14 IO board and Neu2 needs to mount on top of this IO board in order to
15 create complete Edgeble Neural Compute Module 2(Neu2) IO platform.
16
Jagan Teki249a2382022-12-14 23:21:05 +0530[diff] [blame]17config SOC_SPECIFIC_OPTIONS # dummy
18 def_bool y
19 select HAS_CUSTOM_SYS_INIT_SP_ADDR
20
21config ROCKCHIP_BOOT_MODE_REG
22 default 0xfe020200
23
24config ROCKCHIP_STIMER_BASE
25 default 0xff670020
26
27config SYS_SOC
28 default "rv1126"
29
30config CUSTOM_SYS_INIT_SP_ADDR
31 default 0x800000
32
33config SPL_STACK
34 default 0x600000
35
36config SPL_STACK_R_ADDR
37 default 0x800000
38
39config TPL_LDSCRIPT
40 default "arch/arm/mach-rockchip/u-boot-tpl.lds"
41
42config TPL_STACK
43 default 0xff718000
44
45config TPL_SYS_MALLOC_F_LEN
46 default 0x2000
47
48config TPL_TEXT_BASE
49 default 0xff701000
50
51config SYS_MALLOC_F_LEN
52 default 0x2000
53
54config TEXT_BASE
55 default 0x600000
56
Jagan Teki1db421e2022-12-14 23:21:11 +0530[diff] [blame]57source board/edgeble/neural-compute-module-2/Kconfig
58
Jagan Teki249a2382022-12-14 23:21:05 +0530[diff] [blame]59endif