blob: 5dc307370d5c1676288ce19d02d35562e91c76a5 [file] [log] [blame]
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +09001/*
2 * board/renesas/blanche/blanche.c
3 * This file is blanche board support.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#include <common.h>
11#include <malloc.h>
12#include <netdev.h>
13#include <dm.h>
14#include <dm/platform_data/serial_sh.h>
Alex Kiernan9c215492018-04-01 09:22:38 +000015#include <environment.h>
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090016#include <asm/processor.h>
17#include <asm/mach-types.h>
18#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090019#include <linux/errno.h>
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090020#include <asm/arch/sys_proto.h>
21#include <asm/gpio.h>
22#include <asm/arch/rmobile.h>
23#include <asm/arch/rcar-mstp.h>
24#include <asm/arch/mmc.h>
25#include <asm/arch/sh_sdhi.h>
26#include <miiphy.h>
27#include <i2c.h>
28#include <mmc.h>
29#include "qos.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33struct pin_db {
34 u32 addr; /* register address */
35 u32 mask; /* mask value */
36 u32 val; /* setting value */
37};
38
39#define PMMR 0xE6060000
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090040#define GPSR0 0xE6060004
41#define GPSR1 0xE6060008
42#define GPSR4 0xE6060014
43#define GPSR5 0xE6060018
44#define GPSR6 0xE606001C
45#define GPSR7 0xE6060020
46#define GPSR8 0xE6060024
47#define GPSR9 0xE6060028
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090048#define GPSR10 0xE606002C
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090049#define GPSR11 0xE6060030
50#define IPSR6 0xE6060058
51#define PUPR2 0xE6060108
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090052#define PUPR3 0xE606010C
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090053#define PUPR4 0xE6060110
54#define PUPR5 0xE6060114
55#define PUPR7 0xE606011C
56#define PUPR9 0xE6060124
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090057#define PUPR10 0xE6060128
58#define PUPR11 0xE606012C
59
60#define CPG_PLL1CR 0xE6150028
61#define CPG_PLL3CR 0xE61500DC
62
63#define SetREG(x) \
64 writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
65
66#define SetGuardREG(x) \
67{ \
68 u32 val; \
69 val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
70 writel(~val, PMMR); \
71 writel(val, (x)->addr); \
72}
73
74struct pin_db pin_guard[] = {
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090075 { GPSR0, 0xFFFFFFFF, 0x0BFFFFFF },
76 { GPSR1, 0xFFFFFFFF, 0x002FFFFF },
77 { GPSR4, 0xFFFFFFFF, 0x00000FFF },
78 { GPSR5, 0xFFFFFFFF, 0x00010FFF },
79 { GPSR6, 0xFFFFFFFF, 0x00010FFF },
80 { GPSR7, 0xFFFFFFFF, 0x00010FFF },
81 { GPSR8, 0xFFFFFFFF, 0x00010FFF },
82 { GPSR9, 0xFFFFFFFF, 0x00010FFF },
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090083 { GPSR10, 0xFFFFFFFF, 0x04006000 },
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090084 { GPSR11, 0xFFFFFFFF, 0x303FEFE0 },
85 { IPSR6, 0xFFFFFFFF, 0x0002000E },
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090086};
87
88struct pin_db pin_tbl[] = {
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090089 { PUPR2, 0xFFFFFFFF, 0x00000000 },
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090090 { PUPR3, 0xFFFFFFFF, 0x0803FF40 },
masakazu.mochizuki.wd@hitachi.com94fdac32016-05-17 13:53:03 +090091 { PUPR4, 0xFFFFFFFF, 0x0000FFFF },
92 { PUPR5, 0xFFFFFFFF, 0x00010FFF },
93 { PUPR7, 0xFFFFFFFF, 0x0001AFFF },
94 { PUPR9, 0xFFFFFFFF, 0x0001CFFF },
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090095 { PUPR10, 0xFFFFFFFF, 0xC0438001 },
96 { PUPR11, 0xFFFFFFFF, 0x0FC00007 },
97};
98
99void pin_init(void)
100{
101 struct pin_db *db;
102
103 for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
104 SetGuardREG(db);
105 }
106 for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
107 SetREG(db);
108 }
109}
110
111#define s_init_wait(cnt) \
112 ({ \
113 volatile u32 i = 0x10000 * cnt; \
114 while (i > 0) \
115 i--; \
116 })
117
118void s_init(void)
119{
120 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
121 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
122 u32 cpu_type;
123
124 cpu_type = rmobile_get_cpu_type();
125 if (cpu_type == 0x4A) {
126 writel(0x4D000000, CPG_PLL1CR);
127 writel(0x4F000000, CPG_PLL3CR);
128 }
129
130 /* Watchdog init */
131 writel(0xA5A5A500, &rwdt->rwtcsra);
132 writel(0xA5A5A500, &swdt->swtcsra);
133
134 /* QoS(Quality-of-Service) Init */
135 qos_init();
136
137 /* SCIF Init */
138 pin_init();
139
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900140#if defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900141 struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
142 struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
143
144 /* LBSC */
145 writel(0x00000020, &lbsc->cs0ctrl);
146 writel(0x00000020, &lbsc->cs1ctrl);
147 writel(0x00002020, &lbsc->ecs0ctrl);
148 writel(0x00002020, &lbsc->ecs1ctrl);
149
150 writel(0x2A103320, &lbsc->cswcr0);
151 writel(0x2A103320, &lbsc->cswcr1);
152 writel(0x19102110, &lbsc->ecswcr0);
153 writel(0x19102110, &lbsc->ecswcr1);
154
155 /* DBSC3 */
156 s_init_wait(10);
157
158 writel(0x0000A55A, &dbsc3_0->dbpdlck);
159
160 writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
161 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
162 writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
163
164 /* Stop Auto-Calibration */
165 writel(0x00000001, &dbsc3_0->dbpdrga);
166 writel(0x80000000, &dbsc3_0->dbpdrgd);
167
168 writel(0x00000004, &dbsc3_0->dbpdrga);
169 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
170
171 /* PLLCR: PLL Control Register */
172 writel(0x00000006, &dbsc3_0->dbpdrga);
173 writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
174
175 /* DXCCR: DATX8 Common Configuration Register */
176 writel(0x0000000F, &dbsc3_0->dbpdrga);
177 writel(0x00181EE4, &dbsc3_0->dbpdrgd);
178
179 /* DSGCR :DDR System General Configuration Register */
180 writel(0x00000010, &dbsc3_0->dbpdrga);
181 writel(0xF00464DB, &dbsc3_0->dbpdrgd);
182
183 writel(0x00000061, &dbsc3_0->dbpdrga);
184 writel(0x0000008D, &dbsc3_0->dbpdrgd);
185
186 /* Re-Execute ZQ calibration */
187 writel(0x00000001, &dbsc3_0->dbpdrga);
188 writel(0x00000073, &dbsc3_0->dbpdrgd);
189
190 writel(0x00000007, &dbsc3_0->dbkind);
191 writel(0x0F030A02, &dbsc3_0->dbconf0);
192 writel(0x00000001, &dbsc3_0->dbphytype);
193 writel(0x00000000, &dbsc3_0->dbbl);
194
195 writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
196 writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
197 writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
198 writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
199 writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
200 writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
201 writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
202 writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
203 writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
204 writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
205 writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
206 writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
207 writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
208 writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
209 writel(0x00140005, &dbsc3_0->dbtr14);
210 writel(0x00050004, &dbsc3_0->dbtr15);
211 writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
212 writel(0x000C0000, &dbsc3_0->dbtr17);
213 writel(0x00000300, &dbsc3_0->dbtr18);
214 writel(0x00000040, &dbsc3_0->dbtr19);
215 writel(0x00000001, &dbsc3_0->dbrnk0);
216 writel(0x00020001, &dbsc3_0->dbadj0);
217 writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
218 writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
219 writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
220
221 while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
222 writel(0x00000011, &dbsc3_0->dbdficnt);
223
224 /* PGCR1 :PHY General Configuration Register 1 */
225 writel(0x00000003, &dbsc3_0->dbpdrga);
226 writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
227
228 /* PGCR2: PHY General Configuration Registers 2 */
229 writel(0x00000023, &dbsc3_0->dbpdrga);
230 writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
231
232 writel(0x00000011, &dbsc3_0->dbpdrga);
233 writel(0x1000040B, &dbsc3_0->dbpdrgd);
234
235 /* DTPR0 :DRAM Timing Parameters Register 0 */
236 writel(0x00000012, &dbsc3_0->dbpdrga);
237 writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
238
239 /* DTPR1 :DRAM Timing Parameters Register 1 */
240 writel(0x00000013, &dbsc3_0->dbpdrga);
241 writel(0x1A868400, &dbsc3_0->dbpdrgd);
242
243 /* DTPR2 ::DRAM Timing Parameters Register 2 */
244 writel(0x00000014, &dbsc3_0->dbpdrga);
245 writel(0x300214D8, &dbsc3_0->dbpdrgd);
246
247 /* MR0 :Mode Register 0 */
248 writel(0x00000015, &dbsc3_0->dbpdrga);
249 writel(0x00000D70, &dbsc3_0->dbpdrgd);
250
251 /* MR1 :Mode Register 1 */
252 writel(0x00000016, &dbsc3_0->dbpdrga);
253 writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
254
255 /* MR2 :Mode Register 2 */
256 writel(0x00000017, &dbsc3_0->dbpdrga);
257 writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
258
259 /* VREF(ZQCAL) */
260 writel(0x0000001A, &dbsc3_0->dbpdrga);
261 writel(0x910035C7, &dbsc3_0->dbpdrgd);
262
263 /* PGSR0 :PHY General Status Registers 0 */
264 writel(0x00000004, &dbsc3_0->dbpdrga);
265 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
266
267 /* DRAM Init (set MRx etc) */
268 writel(0x00000001, &dbsc3_0->dbpdrga);
269 writel(0x00000181, &dbsc3_0->dbpdrgd);
270
271 /* CKE = H */
272 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
273
274 /* PGSR0 :PHY General Status Registers 0 */
275 writel(0x00000004, &dbsc3_0->dbpdrga);
276 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
277
278 /* RAM ACC Training */
279 writel(0x00000001, &dbsc3_0->dbpdrga);
280 writel(0x0000FE01, &dbsc3_0->dbpdrgd);
281
282 /* Bus control 0 */
283 writel(0x00000000, &dbsc3_0->dbbs0cnt1);
284 /* DDR3 Calibration set */
285 writel(0x01004C20, &dbsc3_0->dbcalcnf);
286 /* DDR3 Calibration timing */
287 writel(0x014000AA, &dbsc3_0->dbcaltr);
288 /* Refresh */
289 writel(0x00000140, &dbsc3_0->dbrfcnf0);
290 writel(0x00081860, &dbsc3_0->dbrfcnf1);
291 writel(0x00010000, &dbsc3_0->dbrfcnf2);
292
293 /* PGSR0 :PHY General Status Registers 0 */
294 writel(0x00000004, &dbsc3_0->dbpdrga);
295 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
296
297 /* Enable Auto-Refresh */
298 writel(0x00000001, &dbsc3_0->dbrfen);
299 /* Permit DDR-Access */
300 writel(0x00000001, &dbsc3_0->dbacen);
301
302 /* This locks the access to the PHY unit registers */
303 writel(0x00000000, &dbsc3_0->dbpdlck);
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900304#endif /* CONFIG_MTD_NOR_FLASH */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900305
306}
307
308#define TMU0_MSTP125 (1 << 25)
309#define SCIF0_MSTP721 (1 << 21)
310#define SDHI0_MSTP314 (1 << 14)
311#define QSPI_MSTP917 (1 << 17)
312
313int board_early_init_f(void)
314{
315 /* TMU0 */
316 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
317 /* SCIF0 */
318 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
319 /* SDHI0 */
320 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
321 /* QSPI */
322 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
323
324 return 0;
325}
326
327DECLARE_GLOBAL_DATA_PTR;
328int board_init(void)
329{
330 /* adress of boot parameters */
331 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
332
333 /* Init PFC controller */
334 r8a7792_pinmux_init();
335
336 gpio_request(GPIO_FN_D0, NULL);
337 gpio_request(GPIO_FN_D1, NULL);
338 gpio_request(GPIO_FN_D2, NULL);
339 gpio_request(GPIO_FN_D3, NULL);
340 gpio_request(GPIO_FN_D4, NULL);
341 gpio_request(GPIO_FN_D5, NULL);
342 gpio_request(GPIO_FN_D6, NULL);
343 gpio_request(GPIO_FN_D7, NULL);
344 gpio_request(GPIO_FN_D8, NULL);
345 gpio_request(GPIO_FN_D9, NULL);
346 gpio_request(GPIO_FN_D10, NULL);
347 gpio_request(GPIO_FN_D11, NULL);
348 gpio_request(GPIO_FN_D12, NULL);
349 gpio_request(GPIO_FN_D13, NULL);
350 gpio_request(GPIO_FN_D14, NULL);
351 gpio_request(GPIO_FN_D15, NULL);
352 gpio_request(GPIO_FN_A0, NULL);
353 gpio_request(GPIO_FN_A1, NULL);
354 gpio_request(GPIO_FN_A2, NULL);
355 gpio_request(GPIO_FN_A3, NULL);
356 gpio_request(GPIO_FN_A4, NULL);
357 gpio_request(GPIO_FN_A5, NULL);
358 gpio_request(GPIO_FN_A6, NULL);
359 gpio_request(GPIO_FN_A7, NULL);
360 gpio_request(GPIO_FN_A8, NULL);
361 gpio_request(GPIO_FN_A9, NULL);
362 gpio_request(GPIO_FN_A10, NULL);
363 gpio_request(GPIO_FN_A11, NULL);
364 gpio_request(GPIO_FN_A12, NULL);
365 gpio_request(GPIO_FN_A13, NULL);
366 gpio_request(GPIO_FN_A14, NULL);
367 gpio_request(GPIO_FN_A15, NULL);
368 gpio_request(GPIO_FN_A16, NULL);
369 gpio_request(GPIO_FN_A17, NULL);
370 gpio_request(GPIO_FN_A18, NULL);
371 gpio_request(GPIO_FN_A19, NULL);
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900372#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900373 gpio_request(GPIO_FN_MOSI_IO0, NULL);
374 gpio_request(GPIO_FN_MISO_IO1, NULL);
375 gpio_request(GPIO_FN_IO2, NULL);
376 gpio_request(GPIO_FN_IO3, NULL);
377 gpio_request(GPIO_FN_SPCLK, NULL);
378 gpio_request(GPIO_FN_SSL, NULL);
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900379#else /* CONFIG_MTD_NOR_FLASH */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900380 gpio_request(GPIO_FN_A20, NULL);
381 gpio_request(GPIO_FN_A21, NULL);
382 gpio_request(GPIO_FN_A22, NULL);
383 gpio_request(GPIO_FN_A23, NULL);
384 gpio_request(GPIO_FN_A24, NULL);
385 gpio_request(GPIO_FN_A25, NULL);
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900386#endif /* CONFIG_MTD_NOR_FLASH */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900387
388 gpio_request(GPIO_FN_CS1_A26, NULL);
389 gpio_request(GPIO_FN_EX_CS0, NULL);
390 gpio_request(GPIO_FN_EX_CS1, NULL);
391 gpio_request(GPIO_FN_BS, NULL);
392 gpio_request(GPIO_FN_RD, NULL);
393 gpio_request(GPIO_FN_WE0, NULL);
394 gpio_request(GPIO_FN_WE1, NULL);
395 gpio_request(GPIO_FN_EX_WAIT0, NULL);
396 gpio_request(GPIO_FN_IRQ0, NULL);
397 gpio_request(GPIO_FN_IRQ2, NULL);
398 gpio_request(GPIO_FN_IRQ3, NULL);
399 gpio_request(GPIO_FN_CS0, NULL);
400
401 /* Init timer */
402 timer_init();
403
404 return 0;
405}
406
407/*
408 Added for BLANCHE(R-CarV2H board)
409*/
410int board_eth_init(bd_t *bis)
411{
412 int rc = 0;
413
414#ifdef CONFIG_SMC911X
415#define STR_ENV_ETHADDR "ethaddr"
416
417 struct eth_device *dev;
418 uchar eth_addr[6];
419
420 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
421
Simon Glass399a9ce2017-08-03 12:22:14 -0600422 if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900423 dev = eth_get_dev_by_index(0);
424 if (dev) {
Simon Glass8551d552017-08-03 12:22:11 -0600425 eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900426 } else {
427 printf("blanche: Couldn't get eth device\n");
428 rc = -1;
429 }
430 }
431
432#endif
433
434 return rc;
435}
436
437int board_mmc_init(bd_t *bis)
438{
439 int ret = -ENODEV;
440
441#ifdef CONFIG_SH_SDHI
442 gpio_request(GPIO_FN_SD0_DAT0, NULL);
443 gpio_request(GPIO_FN_SD0_DAT1, NULL);
444 gpio_request(GPIO_FN_SD0_DAT2, NULL);
445 gpio_request(GPIO_FN_SD0_DAT3, NULL);
446 gpio_request(GPIO_FN_SD0_CLK, NULL);
447 gpio_request(GPIO_FN_SD0_CMD, NULL);
448 gpio_request(GPIO_FN_SD0_CD, NULL);
449
450 gpio_request(GPIO_GP_11_12, NULL);
451 gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
452
453
454 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
455 SH_SDHI_QUIRK_16BIT_BUF);
456
457 if (ret)
458 return ret;
459#endif
460 return ret;
461}
462
463int dram_init(void)
464{
465 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
466 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
467
468 return 0;
469}
470
471const struct rmobile_sysinfo sysinfo = {
472 CONFIG_RMOBILE_BOARD_STRING
473};
474
475void reset_cpu(ulong addr)
476{
477}
478
479static const struct sh_serial_platdata serial_platdata = {
480 .base = SCIF0_BASE,
481 .type = PORT_SCIF,
482 .clk = 14745600,
483 .clk_mode = EXT_CLK,
484};
485
486U_BOOT_DEVICE(blanche_serials) = {
487 .name = "serial_sh",
488 .platdata = &serial_platdata,
489};