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git01.mediatek.com / filogic / uboot / 9bffec6d279c26ac8173c9cb0716bf85eec763fa / . / arch / sandbox / dts / test.dts
blob: 3790b4c5208e96f7e3dc4c2a0a0b0e06bd9e0004 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]79 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]80 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]81 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]82 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]83 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]84 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]85 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
86 <0>, <&gpio_a 12>;
87 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
88 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
89 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]90 int-value = <1234>;
91 uint-value = <(-1234)>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]92 };
93
94 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]95 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]96 compatible = "not,compatible";
97 };
98
99 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]100 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]101 };
102
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]103 backlight: backlight {
104 compatible = "pwm-backlight";
105 enable-gpios = <&gpio_a 1>;
106 power-supply = <&ldo_1>;
107 pwms = <&pwm 0 1000>;
108 default-brightness-level = <5>;
109 brightness-levels = <0 16 32 64 128 170 202 234 255>;
110 };
111
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]112 bind-test {
113 bind-test-child1 {
114 compatible = "sandbox,phy";
115 #phy-cells = <1>;
116 };
117
118 bind-test-child2 {
119 compatible = "simple-bus";
120 };
121 };
122
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]123 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]124 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]125 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]126 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]127 ping-add = <3>;
128 };
129
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]130 phy_provider0: gen_phy@0 {
131 compatible = "sandbox,phy";
132 #phy-cells = <1>;
133 };
134
135 phy_provider1: gen_phy@1 {
136 compatible = "sandbox,phy";
137 #phy-cells = <0>;
138 broken;
139 };
140
141 gen_phy_user: gen_phy_user {
142 compatible = "simple-bus";
143 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
144 phy-names = "phy1", "phy2", "phy3";
145 };
146
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]147 some-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]150 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]151 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]152 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]153 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]154 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]155 compatible = "denx,u-boot-fdt-test";
156 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]157 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]158 ping-add = <5>;
159 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]160 c-test@0 {
161 compatible = "denx,u-boot-fdt-test";
162 reg = <0>;
163 ping-expect = <6>;
164 ping-add = <6>;
165 };
166 c-test@1 {
167 compatible = "denx,u-boot-fdt-test";
168 reg = <1>;
169 ping-expect = <7>;
170 ping-add = <7>;
171 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]172 };
173
174 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]176 ping-expect = <6>;
177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
181 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]182 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]183 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]184 ping-add = <6>;
185 compatible = "google,another-fdt-test";
186 };
187
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]188 f-test {
189 compatible = "denx,u-boot-fdt-test";
190 };
191
192 g-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]196 h-test {
197 compatible = "denx,u-boot-fdt-test1";
198 };
199
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]200 clocks {
201 clk_fixed: clk-fixed {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <1234>;
205 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]206 };
207
208 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]209 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]210 #clock-cells = <1>;
211 };
212
213 clk-test {
214 compatible = "sandbox,clk-test";
215 clocks = <&clk_fixed>,
216 <&clk_sandbox 1>,
217 <&clk_sandbox 0>;
218 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]219 };
220
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]221 eth@10002000 {
222 compatible = "sandbox,eth";
223 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]224 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]225 };
226
227 eth_5: eth@10003000 {
228 compatible = "sandbox,eth";
229 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]230 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]231 };
232
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]233 eth_3: sbe5 {
234 compatible = "sandbox,eth";
235 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]236 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]237 };
238
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]239 eth@10004000 {
240 compatible = "sandbox,eth";
241 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]242 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]243 };
244
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]245 firmware {
246 sandbox_firmware: sandbox-firmware {
247 compatible = "sandbox,firmware";
248 };
249 };
250
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]251 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]252 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]253 gpio-controller;
254 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]255 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]256 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]257 };
258
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]259 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]260 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]261 gpio-controller;
262 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]263 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]264 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]265 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]266
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]267 i2c@0 {
268 #address-cells = <1>;
269 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]270 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]271 compatible = "sandbox,i2c";
272 clock-frequency = <100000>;
273 eeprom@2c {
274 reg = <0x2c>;
275 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]276 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]277 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]278
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]279 rtc_0: rtc@43 {
280 reg = <0x43>;
281 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]282 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]283 };
284
285 rtc_1: rtc@61 {
286 reg = <0x61>;
287 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]288 sandbox,emul = <&emul1>;
289 };
290
291 i2c_emul: emul {
292 reg = <0xff>;
293 compatible = "sandbox,i2c-emul-parent";
294 emul_eeprom: emul-eeprom {
295 compatible = "sandbox,i2c-eeprom";
296 sandbox,filename = "i2c.bin";
297 sandbox,size = <256>;
298 };
299 emul0: emul0 {
300 compatible = "sandbox,i2c-rtc";
301 };
302 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]303 compatible = "sandbox,i2c-rtc";
304 };
305 };
306
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]307 sandbox_pmic: sandbox_pmic {
308 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]309 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]310 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]311
312 mc34708: pmic@41 {
313 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]314 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]315 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]316 };
317
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]318 adc@0 {
319 compatible = "sandbox,adc";
320 vdd-supply = <&buck2>;
321 vss-microvolts = <0>;
322 };
323
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]324 lcd {
325 u-boot,dm-pre-reloc;
326 compatible = "sandbox,lcd-sdl";
327 xres = <1366>;
328 yres = <768>;
329 };
330
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]331 leds {
332 compatible = "gpio-leds";
333
334 iracibble {
335 gpios = <&gpio_a 1 0>;
336 label = "sandbox:red";
337 };
338
339 martinet {
340 gpios = <&gpio_a 2 0>;
341 label = "sandbox:green";
342 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]343
344 default_on {
345 gpios = <&gpio_a 5 0>;
346 label = "sandbox:default_on";
347 default-state = "on";
348 };
349
350 default_off {
351 gpios = <&gpio_a 6 0>;
352 label = "sandbox:default_off";
353 default-state = "off";
354 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]355 };
356
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]357 mbox: mbox {
358 compatible = "sandbox,mbox";
359 #mbox-cells = <1>;
360 };
361
362 mbox-test {
363 compatible = "sandbox,mbox-test";
364 mboxes = <&mbox 100>, <&mbox 1>;
365 mbox-names = "other", "test";
366 };
367
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]368 cpu-test1 {
369 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]370 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]371 };
372
373 cpu-test2 {
374 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]375 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]376 };
377
378 cpu-test3 {
379 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]380 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]381 };
382
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]383 i2s: i2s {
384 compatible = "sandbox,i2s";
385 #sound-dai-cells = <1>;
386 };
387
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]388 misc-test {
389 compatible = "sandbox,misc_sandbox";
390 };
391
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]392 mmc2 {
393 compatible = "sandbox,mmc";
394 };
395
396 mmc1 {
397 compatible = "sandbox,mmc";
398 };
399
400 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]401 compatible = "sandbox,mmc";
402 };
403
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]404 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]405 compatible = "sandbox,pci";
406 device_type = "pci";
407 #address-cells = <3>;
408 #size-cells = <2>;
409 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
410 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]411 pci@0,0 {
412 compatible = "pci-generic";
413 reg = <0x0000 0 0 0 0>;
414 emul@0,0 {
415 compatible = "sandbox,swap-case";
416 };
417 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]418 pci@1f,0 {
419 compatible = "pci-generic";
420 reg = <0xf800 0 0 0 0>;
421 emul@1f,0 {
422 compatible = "sandbox,swap-case";
423 };
424 };
425 };
426
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]427 pci1: pci-controller1 {
428 compatible = "sandbox,pci";
429 device_type = "pci";
430 #address-cells = <3>;
431 #size-cells = <2>;
432 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
433 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]434 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]435 0x0c 0x00 0x1234 0x5678
436 0x10 0x00 0x1234 0x5678>;
437 pci@10,0 {
438 reg = <0x8000 0 0 0 0>;
439 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]440 };
441
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]442 pci2: pci-controller2 {
443 compatible = "sandbox,pci";
444 device_type = "pci";
445 #address-cells = <3>;
446 #size-cells = <2>;
447 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
448 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
449 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
450 pci@1f,0 {
451 compatible = "pci-generic";
452 reg = <0xf800 0 0 0 0>;
453 emul@1f,0 {
454 compatible = "sandbox,swap-case";
455 };
456 };
457 };
458
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]459 probing {
460 compatible = "simple-bus";
461 test1 {
462 compatible = "denx,u-boot-probe-test";
463 };
464
465 test2 {
466 compatible = "denx,u-boot-probe-test";
467 };
468
469 test3 {
470 compatible = "denx,u-boot-probe-test";
471 };
472
473 test4 {
474 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]475 first-syscon = <&syscon0>;
476 second-sys-ctrl = <&another_system_controller>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]477 };
478 };
479
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]480 pwrdom: power-domain {
481 compatible = "sandbox,power-domain";
482 #power-domain-cells = <1>;
483 };
484
485 power-domain-test {
486 compatible = "sandbox,power-domain-test";
487 power-domains = <&pwrdom 2>;
488 };
489
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]490 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]491 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]492 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]493 };
494
495 pwm2 {
496 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]497 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]498 };
499
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]500 ram {
501 compatible = "sandbox,ram";
502 };
503
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]504 reset@0 {
505 compatible = "sandbox,warm-reset";
506 };
507
508 reset@1 {
509 compatible = "sandbox,reset";
510 };
511
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]512 resetc: reset-ctl {
513 compatible = "sandbox,reset-ctl";
514 #reset-cells = <1>;
515 };
516
517 reset-ctl-test {
518 compatible = "sandbox,reset-ctl-test";
519 resets = <&resetc 100>, <&resetc 2>;
520 reset-names = "other", "test";
521 };
522
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]523 rproc_1: rproc@1 {
524 compatible = "sandbox,test-processor";
525 remoteproc-name = "remoteproc-test-dev1";
526 };
527
528 rproc_2: rproc@2 {
529 compatible = "sandbox,test-processor";
530 internal-memory-mapped;
531 remoteproc-name = "remoteproc-test-dev2";
532 };
533
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]534 panel {
535 compatible = "simple-panel";
536 backlight = <&backlight 0 100>;
537 };
538
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]539 smem@0 {
540 compatible = "sandbox,smem";
541 };
542
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]543 sound {
544 compatible = "sandbox,sound";
545 cpu {
546 sound-dai = <&i2s 0>;
547 };
548
549 codec {
550 sound-dai = <&audio 0>;
551 };
552 };
553
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]554 spi@0 {
555 #address-cells = <1>;
556 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]557 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]558 compatible = "sandbox,spi";
559 cs-gpios = <0>, <&gpio_a 0>;
560 spi.bin@0 {
561 reg = <0>;
562 compatible = "spansion,m25p16", "spi-flash";
563 spi-max-frequency = <40000000>;
564 sandbox,filename = "spi.bin";
565 };
566 };
567
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]568 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]569 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]570 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]571 };
572
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]573 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]574 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]575 reg = <0x20 5
576 0x28 6
577 0x30 7
578 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]579 };
580
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]581 syscon@2 {
582 compatible = "simple-mfd", "syscon";
583 reg = <0x40 5
584 0x48 6
585 0x50 7
586 0x58 8>;
587 };
588
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]589 timer {
590 compatible = "sandbox,timer";
591 clock-frequency = <1000000>;
592 };
593
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]594 tpm2 {
595 compatible = "sandbox,tpm2";
596 };
597
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]598 uart0: serial {
599 compatible = "sandbox,serial";
600 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]601 };
602
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]603 usb_0: usb@0 {
604 compatible = "sandbox,usb";
605 status = "disabled";
606 hub {
607 compatible = "sandbox,usb-hub";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 flash-stick {
611 reg = <0>;
612 compatible = "sandbox,usb-flash";
613 };
614 };
615 };
616
617 usb_1: usb@1 {
618 compatible = "sandbox,usb";
619 hub {
620 compatible = "usb-hub";
621 usb,device-class = <9>;
622 hub-emul {
623 compatible = "sandbox,usb-hub";
624 #address-cells = <1>;
625 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]626 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]627 reg = <0>;
628 compatible = "sandbox,usb-flash";
629 sandbox,filepath = "testflash.bin";
630 };
631
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]632 flash-stick@1 {
633 reg = <1>;
634 compatible = "sandbox,usb-flash";
635 sandbox,filepath = "testflash1.bin";
636 };
637
638 flash-stick@2 {
639 reg = <2>;
640 compatible = "sandbox,usb-flash";
641 sandbox,filepath = "testflash2.bin";
642 };
643
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]644 keyb@3 {
645 reg = <3>;
646 compatible = "sandbox,usb-keyb";
647 };
648
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]649 };
650 };
651 };
652
653 usb_2: usb@2 {
654 compatible = "sandbox,usb";
655 status = "disabled";
656 };
657
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]658 spmi: spmi@0 {
659 compatible = "sandbox,spmi";
660 #address-cells = <0x1>;
661 #size-cells = <0x1>;
662 pm8916@0 {
663 compatible = "qcom,spmi-pmic";
664 reg = <0x0 0x1>;
665 #address-cells = <0x1>;
666 #size-cells = <0x1>;
667
668 spmi_gpios: gpios@c000 {
669 compatible = "qcom,pm8916-gpio";
670 reg = <0xc000 0x400>;
671 gpio-controller;
672 gpio-count = <4>;
673 #gpio-cells = <2>;
674 gpio-bank-name="spmi";
675 };
676 };
677 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]678
679 wdt0: wdt@0 {
680 compatible = "sandbox,wdt";
681 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]682
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]683 axi: axi@0 {
684 compatible = "sandbox,axi";
685 #address-cells = <0x1>;
686 #size-cells = <0x1>;
687 store@0 {
688 compatible = "sandbox,sandbox_store";
689 reg = <0x0 0x400>;
690 };
691 };
692
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]693 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]694 #address-cells = <1>;
695 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]696 chosen-test {
697 compatible = "denx,u-boot-fdt-test";
698 reg = <9 1>;
699 };
700 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]701
702 translation-test@8000 {
703 compatible = "simple-bus";
704 reg = <0x8000 0x4000>;
705
706 #address-cells = <0x2>;
707 #size-cells = <0x1>;
708
709 ranges = <0 0x0 0x8000 0x1000
710 1 0x100 0x9000 0x1000
711 2 0x200 0xA000 0x1000
712 3 0x300 0xB000 0x1000
713 >;
714
715 dev@0,0 {
716 compatible = "denx,u-boot-fdt-dummy";
717 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]718 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]719 };
720
721 dev@1,100 {
722 compatible = "denx,u-boot-fdt-dummy";
723 reg = <1 0x100 0x1000>;
724
725 };
726
727 dev@2,200 {
728 compatible = "denx,u-boot-fdt-dummy";
729 reg = <2 0x200 0x1000>;
730 };
731
732
733 noxlatebus@3,300 {
734 compatible = "simple-bus";
735 reg = <3 0x300 0x1000>;
736
737 #address-cells = <0x1>;
738 #size-cells = <0x0>;
739
740 dev@42 {
741 compatible = "denx,u-boot-fdt-dummy";
742 reg = <0x42>;
743 };
744 };
745 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]746
747 osd {
748 compatible = "sandbox,sandbox_osd";
749 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]750
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]751 board {
752 compatible = "sandbox,board_sandbox";
753 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]754
755 sandbox_tee {
756 compatible = "sandbox,tee";
757 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]758
759 sandbox_virtio1 {
760 compatible = "sandbox,virtio1";
761 };
762
763 sandbox_virtio2 {
764 compatible = "sandbox,virtio2";
765 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]766
767 pinctrl {
768 compatible = "sandbox,pinctrl";
769 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]770
771 hwspinlock@0 {
772 compatible = "sandbox,hwspinlock";
773 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]774
775 dma: dma {
776 compatible = "sandbox,dma";
777 #dma-cells = <1>;
778
779 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
780 dma-names = "m2m", "tx0", "rx0";
781 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]782};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]783
784#include "sandbox_pmic.dtsi"