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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Stephen Warren6422ace2015-10-23 10:50:49 -06002/*
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Stephen Warren6422ace2015-10-23 10:50:49 -06004 */
5
6#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
7#define _TEGRA_XUSB_PADCTL_COMMON_H_
8
Stephen Warren6422ace2015-10-23 10:50:49 -06009#include <fdtdec.h>
Simon Glasscf0c6e22017-07-25 08:29:59 -060010#include <dm/ofnode.h>
Stephen Warren6422ace2015-10-23 10:50:49 -060011
12#include <asm/io.h>
13#include <asm/arch-tegra/xusb-padctl.h>
Simon Glasscf0c6e22017-07-25 08:29:59 -060014#include <linux/ioport.h>
Stephen Warren6422ace2015-10-23 10:50:49 -060015
16struct tegra_xusb_padctl_lane {
17 const char *name;
18
19 unsigned int offset;
20 unsigned int shift;
21 unsigned int mask;
22 unsigned int iddq;
23
24 const unsigned int *funcs;
25 unsigned int num_funcs;
26};
27
28struct tegra_xusb_phy_ops {
29 int (*prepare)(struct tegra_xusb_phy *phy);
30 int (*enable)(struct tegra_xusb_phy *phy);
31 int (*disable)(struct tegra_xusb_phy *phy);
32 int (*unprepare)(struct tegra_xusb_phy *phy);
33};
34
35struct tegra_xusb_phy {
Stephen Warrenfbae1972015-10-23 10:50:50 -060036 unsigned int type;
Stephen Warren6422ace2015-10-23 10:50:49 -060037 const struct tegra_xusb_phy_ops *ops;
Stephen Warren6422ace2015-10-23 10:50:49 -060038 struct tegra_xusb_padctl *padctl;
39};
40
41struct tegra_xusb_padctl_pin {
42 const struct tegra_xusb_padctl_lane *lane;
43
44 unsigned int func;
45 int iddq;
46};
47
Stephen Warrene3ba5692015-10-23 10:50:52 -060048#define MAX_GROUPS 5
49#define MAX_PINS 7
Stephen Warren6422ace2015-10-23 10:50:49 -060050
51struct tegra_xusb_padctl_group {
52 const char *name;
53
54 const char *pins[MAX_PINS];
55 unsigned int num_pins;
56
57 const char *func;
58 int iddq;
59};
60
Stephen Warrenfbae1972015-10-23 10:50:50 -060061struct tegra_xusb_padctl_soc {
62 const struct tegra_xusb_padctl_lane *lanes;
63 unsigned int num_lanes;
64 const char *const *functions;
65 unsigned int num_functions;
66 struct tegra_xusb_phy *phys;
67 unsigned int num_phys;
68};
69
Stephen Warren6422ace2015-10-23 10:50:49 -060070struct tegra_xusb_padctl_config {
71 const char *name;
72
73 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
74 unsigned int num_groups;
75};
76
77struct tegra_xusb_padctl {
Stephen Warrenfbae1972015-10-23 10:50:50 -060078 const struct tegra_xusb_padctl_soc *socdata;
79 struct tegra_xusb_padctl_config config;
Simon Glasscf0c6e22017-07-25 08:29:59 -060080 struct resource regs;
Stephen Warren6422ace2015-10-23 10:50:49 -060081 unsigned int enable;
82
Stephen Warren6422ace2015-10-23 10:50:49 -060083};
Stephen Warrenfbae1972015-10-23 10:50:50 -060084extern struct tegra_xusb_padctl padctl;
Stephen Warren6422ace2015-10-23 10:50:49 -060085
86static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
87 unsigned long offset)
88{
89 return readl(padctl->regs.start + offset);
90}
91
92static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
93 u32 value, unsigned long offset)
94{
95 writel(value, padctl->regs.start + offset);
96}
97
Simon Glasscf0c6e22017-07-25 08:29:59 -060098int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
99 const struct tegra_xusb_padctl_soc *socdata);
Stephen Warren6422ace2015-10-23 10:50:49 -0600100
101#endif