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Patrick Delaunaye7f435d2018-07-09 15:17:22 +02001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include "stm32mp157c-ed1-u-boot.dtsi"
7
8/ {
9 aliases {
Patrick Delaunay1b58b552019-04-12 14:38:28 +020010 gpio26 = &stmfx_pinctrl;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +020011 i2c1 = &i2c2;
12 i2c4 = &i2c5;
Patrick Delaunay1b58b552019-04-12 14:38:28 +020013 pinctrl2 = &stmfx_pinctrl;
Patrice Chotard00442d02019-02-12 16:50:38 +010014 spi0 = &qspi;
Patrick Delaunay58bc0cd2019-03-29 15:42:23 +010015 usb0 = &usbotg_hs;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +020016 };
Sughosh Ganu7f08d272022-10-21 18:15:57 +053017
18 fwu-mdata {
19 compatible = "u-boot,fwu-mdata-gpt";
20 fwu-mdata-store = <&sdmmc1>;
21 };
Patrick Delaunaye7f435d2018-07-09 15:17:22 +020022};
23
24&flash0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070025 bootph-pre-ram;
Patrice Chotard4cacdd12023-06-08 17:16:42 +020026 partitions {
27 compatible = "fixed-partitions";
28 #address-cells = <1>;
29 #size-cells = <1>;
30
Patrick Delaunay4c6fcbc2024-01-15 15:05:57 +010031#if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL)
Patrice Chotard4cacdd12023-06-08 17:16:42 +020032 partition@0 {
33 label = "fsbl1";
34 reg = <0x00000000 0x00040000>;
35 };
36 partition@80000 {
37 label = "fsbl2";
38 reg = <0x00040000 0x00040000>;
39 };
40 partition@100000 {
41 label = "ssbl";
42 reg = <0x00080000 0x00200000>;
43 };
44 partition@280000 {
45 label = "u-boot-env";
46 reg = <0x00280000 0x00080000>;
47 };
48 partition@300000 {
49 label = "nor-user";
50 reg = <0x00300000 0x03d00000>;
51 };
52#else
53 partition@0 {
54 label = "fsbl1";
55 reg = <0x00000000 0x00040000>;
56 };
57 partition@40000 {
58 label = "fsbl2";
59 reg = <0x00040000 0x00040000>;
60 };
61 partition@100000 {
62 label = "fip";
63 reg = <0x00080000 0x00400000>;
64 };
65 partition@480000 {
66 label = "u-boot-env";
67 reg = <0x00480000 0x00080000>;
68 };
69 partition@500000 {
70 label = "nor-user";
71 reg = <0x00500000 0x03b00000>;
72 };
73#endif
74 };
Patrick Delaunaye7f435d2018-07-09 15:17:22 +020075};
76
Patrice Chotard4cacdd12023-06-08 17:16:42 +020077&fmc {
78 nand-controller@4,0 {
79 nand@0 {
80 partitions {
81 compatible = "fixed-partitions";
82 #address-cells = <1>;
83 #size-cells = <1>;
84
Patrick Delaunay4c6fcbc2024-01-15 15:05:57 +010085#if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL)
Patrice Chotard4cacdd12023-06-08 17:16:42 +020086 partition@0 {
87 label = "fsbl";
88 reg = <0x00000000 0x00200000>;
89 };
90 partition@200000 {
91 label = "ssbl1";
92 reg = <0x00200000 0x00200000>;
93 };
94 partition@400000 {
95 label = "ssbl2";
96 reg = <0x00400000 0x00200000>;
97 };
98 partition@600000 {
99 label = "UBI";
100 reg = <0x00600000 0x3fa00000>;
101 };
102#else
103 partition@0 {
104 label = "fsbl";
105 reg = <0x00000000 0x00200000>;
106 };
107 partition@200000 {
108 label = "fip1";
109 reg = <0x00200000 0x00400000>;
110 };
111 partition@600000 {
112 label = "fip2";
113 reg = <0x00600000 0x00400000>;
114 };
115 partition@1200000 {
116 label = "UBI";
117 reg = <0x00a00000 0x3f600000>;
118 };
119#endif
120 };
121 };
122 };
123};
124
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200125&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700126 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200127};
128
129&qspi_clk_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700130 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200131 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700132 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200133 };
134};
135
136&qspi_bk1_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700137 bootph-pre-ram;
Marek Vasut3f3375c2023-10-10 01:15:51 +0200138 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700139 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200140 };
Marek Vasut3f3375c2023-10-10 01:15:51 +0200141};
142
143&qspi_cs1_pins_a {
144 bootph-pre-ram;
145 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700146 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200147 };
148};
149
150&qspi_bk2_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700151 bootph-pre-ram;
Marek Vasut3f3375c2023-10-10 01:15:51 +0200152 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700153 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200154 };
Marek Vasut3f3375c2023-10-10 01:15:51 +0200155};
156
157&qspi_cs2_pins_a {
158 bootph-pre-ram;
159 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700160 bootph-pre-ram;
Patrick Delaunaye7f435d2018-07-09 15:17:22 +0200161 };
162};