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git01.mediatek.com / filogic / uboot / 9be5750e6eb38e1e79173ee3a5ade276df8a4801 / . / include / configs / adp-ag102.h
blob: 39f7a3cd46fead68a98a8ac74c28fe43b499321e [file] [log] [blame]
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]1/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include <asm/arch/ag102.h>
12
13/*
14 * CPU and Board Configuration Options
15 */
16#define CONFIG_ADP_AG102
17
18#define CONFIG_USE_INTERRUPT
19
20#define CONFIG_SKIP_LOWLEVEL_INIT
21
22#ifndef CONFIG_SKIP_LOWLEVEL_INIT
23#define CONFIG_MEM_REMAP
24#endif
25
26#ifdef CONFIG_SKIP_LOWLEVEL_INIT
27#define CONFIG_SYS_TEXT_BASE 0x04200000
28#else
29#define CONFIG_SYS_TEXT_BASE 0x00000000
30#endif
31
32/*
33 * Timer
34 */
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]35#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
36#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
37
38/*
39 * Use Externel CLOCK or PCLK
40 */
41#undef CONFIG_FTRTC010_EXTCLK
42
43#ifndef CONFIG_FTRTC010_EXTCLK
44#define CONFIG_FTRTC010_PCLK
45#endif
46
47#ifdef CONFIG_FTRTC010_EXTCLK
48#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
49#else
50#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
51#endif
52
53#define TIMER_LOAD_VAL 0xffffffff
54
55/*
56 * Real Time Clock
57 */
58#define CONFIG_RTC_FTRTC010
59
60/*
61 * Real Time Clock Divider
62 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
63 */
64#define OSC_5MHZ (5*1000000)
65#define OSC_CLK (2*OSC_5MHZ)
66#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
67
68/*
69 * Serial console configuration
70 */
71
72/* FTUART is a high speed NS 16C550A compatible UART */
73#define CONFIG_BAUDRATE 38400
74#define CONFIG_CONS_INDEX 1
75#define CONFIG_SYS_NS16550
76#define CONFIG_SYS_NS16550_SERIAL
77#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
78#define CONFIG_SYS_NS16550_REG_SIZE -4
79#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
80
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]81/*
82 * Ethernet
83 */
84#define CONFIG_NET_MULTI
85#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
86#define CONFIG_SYS_DISCOVER_PHY
87#define CONFIG_FTGMAC100
88#define CONFIG_FTGMAC100_EGIGA
89
90#define CONFIG_BOOTDELAY 3
91
92/*
93 * SD (MMC) controller
94 */
95#define CONFIG_MMC
96#define CONFIG_CMD_MMC
97#define CONFIG_GENERIC_MMC
98#define CONFIG_DOS_PARTITION
99#define CONFIG_FTSDC010
100#define CONFIG_FTSDC010_NUMBER 1
101#define CONFIG_FTSDC010_SDIO
102#define CONFIG_CMD_FAT
103#define CONFIG_CMD_EXT2
104
105/*
106 * Command line configuration.
107 */
108#include <config_cmd_default.h>
109
110#define CONFIG_CMD_CACHE
111#define CONFIG_CMD_DATE
112#define CONFIG_CMD_PING
113#define CONFIG_CMD_IDE
114#define CONFIG_CMD_FAT
115#define CONFIG_CMD_ELF
116
117#undef CONFIG_CMD_FLASH
118#undef CONFIG_CMD_IMLS
119
120/*
121 * PCI
122 */
123#define CONFIG_PCI
124#define CONFIG_FTPCI100
Gabor Juhosb4458732013-05-30 07:06:12 +0000[diff] [blame]125#define CONFIG_PCI_INDIRECT_BRIDGE
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]126#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
127#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
128#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
129#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
130
131#define CONFIG_PCI_MEM_BUS 0xa0000000
132#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
133#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
134
135#define CONFIG_PCI_IO_BUS 0x90000000
136#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
137#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
138
139/*
140 * USB
141 */
142#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
143#if defined(CONFIG_FTPCI100)
144#define __io /* enable outl & inl */
145#define CONFIG_CMD_USB
146#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
147#define CONFIG_USB_STORAGE
148#define CONFIG_USB_EHCI
149#define CONFIG_PCI_EHCI_DEVICE 0
150#define CONFIG_USB_EHCI_PCI
151#define CONFIG_PREBOOT "usb start;"
152#endif /* #if defiend(CONFIG_FTPCI100) */
153#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
154
155/*
156 * IDE/ATA stuff
157 */
158#define __io
159#define CONFIG_IDE_AHB
160#define CONFIG_IDE_FTIDE020
161
162#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
163#undef CONFIG_IDE_LED /* no led for ide supported */
164#define CONFIG_IDE_RESET 1 /* reset for ide supported */
165#define CONFIG_IDE_PREINIT 1 /* preinit for ide */
166
167/* max: 2 IDE busses */
168#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
169/* max: 2 drives per IDE bus */
170#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
171
172#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
173#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
174#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
175
176#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
177#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
178#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
179
180#define CONFIG_MAC_PARTITION
181#define CONFIG_DOS_PARTITION
182#define CONFIG_SUPPORT_VFAT
183
184/*
185 * Miscellaneous configurable options
186 */
187#define CONFIG_SYS_LONGHELP /* undef to save memory */
188#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
189#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
190
191/* Print Buffer Size */
192#define CONFIG_SYS_PBSIZE \
193 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
194
195/* max number of command args */
196#define CONFIG_SYS_MAXARGS 16
197
198/* Boot Argument Buffer Size */
199#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
200
201/*
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]202 * Size of malloc() pool
203 */
204#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
205
206/*
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]207 * AHB Controller configuration
208 */
209#define CONFIG_FTAHBC020S
210
211#ifdef CONFIG_FTAHBC020S
212#include <faraday/ftahbc020s.h>
213
214/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
215#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
216
217/*
218 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
219 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
220 * in C language.
221 */
222#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
223 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
224 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
225#endif
226
227/*
228 * Watchdog
229 */
230#define CONFIG_FTWDT010_WATCHDOG
231
232/*
233 * PCU Power Control Unit configuration
234 */
235#define CONFIG_ANDES_PCU
236
237#ifdef CONFIG_ANDES_PCU
238#include <andestech/andes_pcu.h>
239
240#endif
241
242/*
243 * DDR DRAM controller configuration
244 */
245#define CONFIG_DWCDDR21MCTL
246
247#ifdef CONFIG_DWCDDR21MCTL
248#include <synopsys/dwcddr21mctl.h>
249/* DCR:
250 * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
251 * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
252 * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
253 * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
254 * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
255 */
256#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
257#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \
258 DWCDDR21MCTL_CCR_DFTLM(0x4) | \
259 DWCDDR21MCTL_CCR_HOSTEN(0x1))
260
261/* 0x04: 0x000020d4 */
262#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
263
264/* 0x08: 0x0000000f */
265#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
266
267/* 0x10: 0x00034812 */
268#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \
269 DWCDDR21MCTL_DRR_TRFPRD(0x0348))
270/* 0x24 */
271#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
272
273/* 0x4c: 0x00000040 */
274#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
275
276/* 0x5c: 0x000055CF */
277#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
278
279/* 0xa4: 0x00100000 */
280#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \
281 DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
282 DWCDDR21MCTL_DTAR_DTCOL(0x0))
283/* 0x1f0: 0x00000852 */
284#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \
285 DWCDDR21MCTL_MR_CL(0x5) | \
286 DWCDDR21MCTL_MR_BL(0x2))
287#endif
288
289/*
290 * Physical Memory Map
291 */
292#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
293#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
294#if defined(CONFIG_MEM_REMAP)
295#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
296#endif
297#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
298#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
299#endif
300
301#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
302#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
303
304#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
305
306#ifdef CONFIG_MEM_REMAP
307#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
308 GENERATED_GBL_DATA_SIZE)
309#else
310#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
311 GENERATED_GBL_DATA_SIZE)
312#endif /* CONFIG_MEM_REMAP */
313
314/*
315 * Load address and memory test area should agree with
316 * board/faraday/a320/config.mk
317 * Be careful not to overwrite U-boot itself.
318 */
319#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
320
321/* memtest works on 63 MB in DRAM */
322#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
323#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
324
325/*
326 * Static memory controller configuration
327 */
328
329/*
330 * FLASH and environment organization
331 */
332#define CONFIG_SYS_NO_FLASH
333
334/*
335 * Env Storage Settings
336 */
337#define CONFIG_ENV_IS_NOWHERE
338#define CONFIG_ENV_SIZE 4096
339
340#endif /* __CONFIG_H */