blob: 891b762946bb067337c677641ea7e6628f83fce7 [file] [log] [blame]
Paweł Anikiel5ee903d2022-06-17 12:47:20 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2022 Google LLC
4 */
5#ifndef __SOCFGPA_CHAMELEONV3_H__
6#define __SOCFGPA_CHAMELEONV3_H__
7
8#include <asm/arch/base_addr_a10.h>
9
10#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
11
12/*
13 * U-Boot general configurations
14 */
15
16/* Memory configurations */
17#define PHYS_SDRAM_1_SIZE 0x40000000
18
19/*
20 * Serial / UART configurations
21 */
22#define CONFIG_SYS_NS16550_MEM32
23#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
24
25#define CONFIG_EXTRA_ENV_SETTINGS \
26 "autoload=no\0" \
27 "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \
28 "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
29 "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
30 "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
31
32/*
33 * L4 OSC1 Timer 0
34 */
35/* reload value when timer count to zero */
36#define TIMER_LOAD_VAL 0xFFFFFFFF
37
38/* SPL memory allocation configuration, this is for FAT implementation */
39#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
40
41/* The rest of the configuration is shared */
42#include <configs/socfpga_common.h>
43
44#endif /* __SOCFGPA_CHAMELEONV3_H__ */