Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 6 | #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ |
| 7 | #define __ASM_ARCH_MX5_IMX_REGS_H__ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 8 | |
Benoît Thébaudeau | 1da8a7b | 2012-08-13 07:27:58 +0000 | [diff] [blame] | 9 | #define ARCH_MXC |
| 10 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 11 | #if defined(CONFIG_MX51) |
Shawn Guo | bc08e7e | 2010-10-28 10:13:15 +0800 | [diff] [blame] | 12 | #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ |
Fabio Estevam | d81a454 | 2012-05-15 08:01:16 +0000 | [diff] [blame] | 13 | #define IPU_SOC_BASE_ADDR 0x40000000 |
| 14 | #define IPU_SOC_OFFSET 0x1E000000 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 15 | #define SPBA0_BASE_ADDR 0x70000000 |
| 16 | #define AIPS1_BASE_ADDR 0x73F00000 |
| 17 | #define AIPS2_BASE_ADDR 0x83F00000 |
| 18 | #define CSD0_BASE_ADDR 0x90000000 |
| 19 | #define CSD1_BASE_ADDR 0xA0000000 |
| 20 | #define NFC_BASE_ADDR_AXI 0xCFFF0000 |
Fabio Estevam | 4ce3624 | 2011-06-07 07:02:50 +0000 | [diff] [blame] | 21 | #define CS1_BASE_ADDR 0xB8000000 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 22 | #elif defined(CONFIG_MX53) |
Fabio Estevam | d81a454 | 2012-05-15 08:01:16 +0000 | [diff] [blame] | 23 | #define IPU_SOC_BASE_ADDR 0x18000000 |
| 24 | #define IPU_SOC_OFFSET 0x06000000 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 25 | #define SPBA0_BASE_ADDR 0x50000000 |
| 26 | #define AIPS1_BASE_ADDR 0x53F00000 |
| 27 | #define AIPS2_BASE_ADDR 0x63F00000 |
| 28 | #define CSD0_BASE_ADDR 0x70000000 |
| 29 | #define CSD1_BASE_ADDR 0xB0000000 |
| 30 | #define NFC_BASE_ADDR_AXI 0xF7FF0000 |
| 31 | #define IRAM_BASE_ADDR 0xF8000000 |
Fabio Estevam | 4ce3624 | 2011-06-07 07:02:50 +0000 | [diff] [blame] | 32 | #define CS1_BASE_ADDR 0xF4000000 |
Stefano Babic | d38db76 | 2012-02-22 00:24:36 +0000 | [diff] [blame] | 33 | #define SATA_BASE_ADDR 0x10000000 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 34 | #else |
| 35 | #error "CPU_TYPE not defined" |
| 36 | #endif |
| 37 | |
| 38 | #define IRAM_SIZE 0x00020000 /* 128 KB */ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * SPBA global module enabled #0 |
| 42 | */ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 43 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) |
| 44 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) |
Stefano Babic | 1ca47d9 | 2011-11-22 15:22:39 +0100 | [diff] [blame] | 45 | #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 46 | #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 47 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) |
| 48 | #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) |
| 49 | #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) |
| 50 | #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) |
| 51 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) |
| 52 | #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) |
| 53 | #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) |
| 54 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) |
| 55 | |
| 56 | /* |
| 57 | * AIPS 1 |
| 58 | */ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 59 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) |
| 60 | #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) |
| 61 | #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) |
| 62 | #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) |
| 63 | #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) |
| 64 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) |
| 65 | #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) |
| 66 | #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) |
| 67 | #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) |
| 68 | #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) |
| 69 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) |
| 70 | #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) |
| 71 | #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) |
| 72 | #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) |
| 73 | #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) |
Stefano Babic | 1ca47d9 | 2011-11-22 15:22:39 +0100 | [diff] [blame] | 74 | #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) |
| 75 | #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 76 | #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) |
| 77 | #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) |
| 78 | #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) |
| 79 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 80 | #if defined(CONFIG_MX53) |
| 81 | #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) |
| 82 | #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) |
| 83 | #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) |
Troy Kisky | 6dd97be | 2012-07-19 08:18:24 +0000 | [diff] [blame] | 84 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) |
Stefano Babic | a4dd6df | 2012-02-22 00:24:33 +0000 | [diff] [blame] | 85 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 86 | #endif |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 87 | /* |
| 88 | * AIPS 2 |
| 89 | */ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 90 | #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) |
| 91 | #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) |
| 92 | #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) |
Marek Vasut | 3c844f3 | 2011-09-23 11:43:47 +0200 | [diff] [blame] | 93 | #ifdef CONFIG_MX53 |
| 94 | #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) |
| 95 | #endif |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 96 | #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) |
| 97 | #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) |
| 98 | #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) |
| 99 | #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 100 | #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 101 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) |
| 102 | #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) |
| 103 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) |
| 104 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) |
| 105 | #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) |
| 106 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) |
| 107 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) |
| 108 | #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) |
| 109 | #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) |
| 110 | #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) |
| 111 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) |
| 112 | #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) |
| 113 | #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) |
| 114 | #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) |
| 115 | #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) |
| 116 | #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) |
| 117 | #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) |
| 118 | #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) |
| 119 | #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) |
| 120 | #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) |
| 121 | #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) |
| 122 | #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) |
| 123 | #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) |
| 124 | #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) |
| 125 | |
Stefano Babic | a4dd6df | 2012-02-22 00:24:33 +0000 | [diff] [blame] | 126 | #if defined(CONFIG_MX53) |
| 127 | #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) |
| 128 | #endif |
| 129 | |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 130 | /* |
Fabio Estevam | 4ce3624 | 2011-06-07 07:02:50 +0000 | [diff] [blame] | 131 | * WEIM CSnGCR1 |
| 132 | */ |
| 133 | #define CSEN 1 |
| 134 | #define SWR (1 << 1) |
| 135 | #define SRD (1 << 2) |
| 136 | #define MUM (1 << 3) |
| 137 | #define WFL (1 << 4) |
| 138 | #define RFL (1 << 5) |
| 139 | #define CRE (1 << 6) |
| 140 | #define CREP (1 << 7) |
| 141 | #define BL(x) (((x) & 0x7) << 8) |
| 142 | #define WC (1 << 11) |
| 143 | #define BCD(x) (((x) & 0x3) << 12) |
| 144 | #define BCS(x) (((x) & 0x3) << 14) |
| 145 | #define DSZ(x) (((x) & 0x7) << 16) |
| 146 | #define SP (1 << 19) |
| 147 | #define CSREC(x) (((x) & 0x7) << 20) |
| 148 | #define AUS (1 << 23) |
| 149 | #define GBC(x) (((x) & 0x7) << 24) |
| 150 | #define WP (1 << 27) |
| 151 | #define PSZ(x) (((x) & 0x0f << 28) |
| 152 | |
| 153 | /* |
| 154 | * WEIM CSnGCR2 |
| 155 | */ |
| 156 | #define ADH(x) (((x) & 0x3)) |
| 157 | #define DAPS(x) (((x) & 0x0f << 4) |
| 158 | #define DAE (1 << 8) |
| 159 | #define DAP (1 << 9) |
| 160 | #define MUX16_BYP (1 << 12) |
| 161 | |
| 162 | /* |
| 163 | * WEIM CSnRCR1 |
| 164 | */ |
| 165 | #define RCSN(x) (((x) & 0x7)) |
| 166 | #define RCSA(x) (((x) & 0x7) << 4) |
| 167 | #define OEN(x) (((x) & 0x7) << 8) |
| 168 | #define OEA(x) (((x) & 0x7) << 12) |
| 169 | #define RADVN(x) (((x) & 0x7) << 16) |
| 170 | #define RAL (1 << 19) |
| 171 | #define RADVA(x) (((x) & 0x7) << 20) |
| 172 | #define RWSC(x) (((x) & 0x3f) << 24) |
| 173 | |
| 174 | /* |
| 175 | * WEIM CSnRCR2 |
| 176 | */ |
| 177 | #define RBEN(x) (((x) & 0x7)) |
| 178 | #define RBE (1 << 3) |
| 179 | #define RBEA(x) (((x) & 0x7) << 4) |
| 180 | #define RL(x) (((x) & 0x3) << 8) |
| 181 | #define PAT(x) (((x) & 0x7) << 12) |
| 182 | #define APR (1 << 15) |
| 183 | |
| 184 | /* |
| 185 | * WEIM CSnWCR1 |
| 186 | */ |
| 187 | #define WCSN(x) (((x) & 0x7)) |
| 188 | #define WCSA(x) (((x) & 0x7) << 3) |
| 189 | #define WEN(x) (((x) & 0x7) << 6) |
| 190 | #define WEA(x) (((x) & 0x7) << 9) |
| 191 | #define WBEN(x) (((x) & 0x7) << 12) |
| 192 | #define WBEA(x) (((x) & 0x7) << 15) |
| 193 | #define WADVN(x) (((x) & 0x7) << 18) |
| 194 | #define WADVA(x) (((x) & 0x7) << 21) |
| 195 | #define WWSC(x) (((x) & 0x3f) << 24) |
| 196 | #define WBED1 (1 << 30) |
| 197 | #define WAL (1 << 31) |
| 198 | |
| 199 | /* |
| 200 | * WEIM CSnWCR2 |
| 201 | */ |
| 202 | #define WBED 1 |
| 203 | |
Fabio Estevam | 4ce3624 | 2011-06-07 07:02:50 +0000 | [diff] [blame] | 204 | /* |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 205 | * CSPI register definitions |
| 206 | */ |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 207 | #define MXC_SPI_BASE_ADDRESSES \ |
| 208 | CSPI1_BASE_ADDR, \ |
| 209 | CSPI2_BASE_ADDR, \ |
| 210 | CSPI3_BASE_ADDR, |
| 211 | |
| 212 | /* |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 213 | * Number of GPIO pins per port |
| 214 | */ |
| 215 | #define GPIO_NUM_PIN 32 |
| 216 | |
| 217 | #define IIM_SREV 0x24 |
| 218 | #define ROM_SI_REV 0x48 |
| 219 | |
| 220 | #define NFC_BUF_SIZE 0x1000 |
| 221 | |
| 222 | /* M4IF */ |
| 223 | #define M4IF_FBPM0 0x40 |
| 224 | #define M4IF_FIDBP 0x48 |
Fabio Estevam | 1b4b5ce | 2013-04-24 14:44:27 +0000 | [diff] [blame] | 225 | #define M4IF_GENP_WEIM_MM_MASK 0x00000001 |
| 226 | #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 227 | |
| 228 | /* Assuming 24MHz input clock with doubler ON */ |
| 229 | /* MFI PDF */ |
David Jander | 088b338 | 2011-07-13 21:11:53 +0000 | [diff] [blame] | 230 | #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) |
| 231 | #define DP_MFD_864 (180 - 1) /* PL Dither mode */ |
| 232 | #define DP_MFN_864 180 |
| 233 | #define DP_MFN_800_DIT 60 /* PL Dither mode */ |
| 234 | |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 235 | #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) |
| 236 | #define DP_MFD_850 (48 - 1) |
| 237 | #define DP_MFN_850 41 |
| 238 | |
| 239 | #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) |
| 240 | #define DP_MFD_800 (3 - 1) |
| 241 | #define DP_MFN_800 1 |
| 242 | |
| 243 | #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) |
| 244 | #define DP_MFD_700 (24 - 1) |
| 245 | #define DP_MFN_700 7 |
| 246 | |
| 247 | #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) |
| 248 | #define DP_MFD_665 (96 - 1) |
| 249 | #define DP_MFN_665 89 |
| 250 | |
| 251 | #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) |
| 252 | #define DP_MFD_532 (24 - 1) |
| 253 | #define DP_MFN_532 13 |
| 254 | |
| 255 | #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) |
| 256 | #define DP_MFD_400 (3 - 1) |
| 257 | #define DP_MFN_400 1 |
| 258 | |
Fabio Estevam | 954f1b2 | 2012-10-15 05:37:16 +0000 | [diff] [blame] | 259 | #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) |
| 260 | #define DP_MFD_455 (48 - 1) |
| 261 | #define DP_MFN_455 23 |
| 262 | |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 263 | #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) |
| 264 | #define DP_MFD_216 (4 - 1) |
| 265 | #define DP_MFN_216 3 |
| 266 | |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 267 | #define IMX_IIM_BASE (IIM_BASE_ADDR) |
| 268 | |
Stefano Babic | ffb5a7b | 2010-09-30 13:11:57 +0200 | [diff] [blame] | 269 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
| 270 | #include <asm/types.h> |
| 271 | |
| 272 | #define __REG(x) (*((volatile u32 *)(x))) |
| 273 | #define __REG16(x) (*((volatile u16 *)(x))) |
| 274 | #define __REG8(x) (*((volatile u8 *)(x))) |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 275 | |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 276 | struct clkctl { |
| 277 | u32 ccr; |
| 278 | u32 ccdr; |
| 279 | u32 csr; |
| 280 | u32 ccsr; |
| 281 | u32 cacrr; |
| 282 | u32 cbcdr; |
| 283 | u32 cbcmr; |
| 284 | u32 cscmr1; |
| 285 | u32 cscmr2; |
| 286 | u32 cscdr1; |
| 287 | u32 cs1cdr; |
| 288 | u32 cs2cdr; |
| 289 | u32 cdcdr; |
| 290 | u32 chsccdr; |
| 291 | u32 cscdr2; |
| 292 | u32 cscdr3; |
| 293 | u32 cscdr4; |
| 294 | u32 cwdr; |
| 295 | u32 cdhipr; |
| 296 | u32 cdcr; |
| 297 | u32 ctor; |
| 298 | u32 clpcr; |
| 299 | u32 cisr; |
| 300 | u32 cimr; |
| 301 | u32 ccosr; |
| 302 | u32 cgpr; |
| 303 | u32 ccgr0; |
| 304 | u32 ccgr1; |
| 305 | u32 ccgr2; |
| 306 | u32 ccgr3; |
| 307 | u32 ccgr4; |
| 308 | u32 ccgr5; |
| 309 | u32 ccgr6; |
Stefano Babic | 115f759 | 2011-07-07 03:37:06 +0000 | [diff] [blame] | 310 | #if defined(CONFIG_MX53) |
| 311 | u32 ccgr7; |
| 312 | #endif |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 313 | u32 cmeor; |
| 314 | }; |
| 315 | |
Stefano Babic | 115f759 | 2011-07-07 03:37:06 +0000 | [diff] [blame] | 316 | /* DPLL registers */ |
| 317 | struct dpll { |
| 318 | u32 dp_ctl; |
| 319 | u32 dp_config; |
| 320 | u32 dp_op; |
| 321 | u32 dp_mfd; |
| 322 | u32 dp_mfn; |
| 323 | u32 dp_mfn_minus; |
| 324 | u32 dp_mfn_plus; |
| 325 | u32 dp_hfs_op; |
| 326 | u32 dp_hfs_mfd; |
| 327 | u32 dp_hfs_mfn; |
| 328 | u32 dp_mfn_togc; |
| 329 | u32 dp_destat; |
| 330 | }; |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 331 | /* WEIM registers */ |
| 332 | struct weim { |
Fabio Estevam | 4ce3624 | 2011-06-07 07:02:50 +0000 | [diff] [blame] | 333 | u32 cs0gcr1; |
| 334 | u32 cs0gcr2; |
| 335 | u32 cs0rcr1; |
| 336 | u32 cs0rcr2; |
| 337 | u32 cs0wcr1; |
| 338 | u32 cs0wcr2; |
| 339 | u32 cs1gcr1; |
| 340 | u32 cs1gcr2; |
| 341 | u32 cs1rcr1; |
| 342 | u32 cs1rcr2; |
| 343 | u32 cs1wcr1; |
| 344 | u32 cs1wcr2; |
| 345 | u32 cs2gcr1; |
| 346 | u32 cs2gcr2; |
| 347 | u32 cs2rcr1; |
| 348 | u32 cs2rcr2; |
| 349 | u32 cs2wcr1; |
| 350 | u32 cs2wcr2; |
| 351 | u32 cs3gcr1; |
| 352 | u32 cs3gcr2; |
| 353 | u32 cs3rcr1; |
| 354 | u32 cs3rcr2; |
| 355 | u32 cs3wcr1; |
| 356 | u32 cs3wcr2; |
| 357 | u32 cs4gcr1; |
| 358 | u32 cs4gcr2; |
| 359 | u32 cs4rcr1; |
| 360 | u32 cs4rcr2; |
| 361 | u32 cs4wcr1; |
| 362 | u32 cs4wcr2; |
| 363 | u32 cs5gcr1; |
| 364 | u32 cs5gcr2; |
| 365 | u32 cs5rcr1; |
| 366 | u32 cs5rcr2; |
| 367 | u32 cs5wcr1; |
| 368 | u32 cs5wcr2; |
| 369 | u32 wcr; |
| 370 | u32 wiar; |
| 371 | u32 ear; |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 372 | }; |
| 373 | |
Fabio Estevam | f8004b1 | 2011-06-07 07:02:51 +0000 | [diff] [blame] | 374 | #if defined(CONFIG_MX51) |
| 375 | struct iomuxc { |
Fabio Estevam | 16e65f6 | 2014-11-14 11:27:21 -0200 | [diff] [blame] | 376 | u32 gpr[2]; |
Fabio Estevam | f8004b1 | 2011-06-07 07:02:51 +0000 | [diff] [blame] | 377 | u32 omux0; |
| 378 | u32 omux1; |
| 379 | u32 omux2; |
| 380 | u32 omux3; |
| 381 | u32 omux4; |
| 382 | }; |
| 383 | #elif defined(CONFIG_MX53) |
| 384 | struct iomuxc { |
Fabio Estevam | 16e65f6 | 2014-11-14 11:27:21 -0200 | [diff] [blame] | 385 | u32 gpr[3]; |
Fabio Estevam | f8004b1 | 2011-06-07 07:02:51 +0000 | [diff] [blame] | 386 | u32 omux0; |
| 387 | u32 omux1; |
| 388 | u32 omux2; |
| 389 | u32 omux3; |
| 390 | u32 omux4; |
| 391 | }; |
| 392 | #endif |
| 393 | |
Martyn Welch | 200b46e | 2017-11-08 15:35:12 +0000 | [diff] [blame] | 394 | #define IOMUXC_GPR2_BITMAP_SPWG 0 |
| 395 | #define IOMUXC_GPR2_BITMAP_JEIDA 1 |
| 396 | |
| 397 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 |
| 398 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) |
| 399 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \ |
| 400 | IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) |
| 401 | #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \ |
| 402 | IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) |
| 403 | |
| 404 | #define IOMUXC_GPR2_DATA_WIDTH_18 0 |
| 405 | #define IOMUXC_GPR2_DATA_WIDTH_24 1 |
| 406 | |
| 407 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 |
| 408 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) |
| 409 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \ |
| 410 | IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) |
| 411 | #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \ |
| 412 | IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) |
| 413 | |
| 414 | #define IOMUXC_GPR2_MODE_DISABLED 0 |
| 415 | #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 |
| 416 | #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 |
| 417 | |
| 418 | #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 |
| 419 | #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
| 420 | #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \ |
| 421 | IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
| 422 | #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \ |
| 423 | IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
| 424 | #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \ |
| 425 | IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) |
| 426 | |
Stefano Babic | 74c5a89 | 2010-08-20 10:42:31 +0200 | [diff] [blame] | 427 | /* System Reset Controller (SRC) */ |
| 428 | struct src { |
| 429 | u32 scr; |
| 430 | u32 sbmr; |
| 431 | u32 srsr; |
| 432 | u32 reserved1[2]; |
| 433 | u32 sisr; |
| 434 | u32 simr; |
| 435 | }; |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 436 | |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 437 | struct srtc_regs { |
| 438 | u32 lpscmr; /* 0x00 */ |
| 439 | u32 lpsclr; /* 0x04 */ |
| 440 | u32 lpsar; /* 0x08 */ |
| 441 | u32 lpsmcr; /* 0x0c */ |
| 442 | u32 lpcr; /* 0x10 */ |
| 443 | u32 lpsr; /* 0x14 */ |
| 444 | u32 lppdr; /* 0x18 */ |
| 445 | u32 lpgr; /* 0x1c */ |
| 446 | u32 hpcmr; /* 0x20 */ |
| 447 | u32 hpclr; /* 0x24 */ |
| 448 | u32 hpamr; /* 0x28 */ |
| 449 | u32 hpalr; /* 0x2c */ |
| 450 | u32 hpcr; /* 0x30 */ |
| 451 | u32 hpisr; /* 0x34 */ |
| 452 | u32 hpienr; /* 0x38 */ |
| 453 | }; |
| 454 | |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 455 | struct iim_regs { |
| 456 | u32 stat; |
| 457 | u32 statm; |
| 458 | u32 err; |
| 459 | u32 emask; |
| 460 | u32 fctl; |
| 461 | u32 ua; |
| 462 | u32 la; |
| 463 | u32 sdat; |
| 464 | u32 prev; |
| 465 | u32 srev; |
Benoît Thébaudeau | fa7e395 | 2013-04-23 10:17:38 +0000 | [diff] [blame] | 466 | u32 prg_p; |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 467 | u32 scs0; |
| 468 | u32 scs1; |
| 469 | u32 scs2; |
| 470 | u32 scs3; |
| 471 | u32 res0[0x1f1]; |
| 472 | struct fuse_bank { |
| 473 | u32 fuse_regs[0x20]; |
| 474 | u32 fuse_rsvd[0xe0]; |
Benoît Thébaudeau | fa7e395 | 2013-04-23 10:17:38 +0000 | [diff] [blame] | 475 | #if defined(CONFIG_MX51) |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 476 | } bank[4]; |
Benoît Thébaudeau | fa7e395 | 2013-04-23 10:17:38 +0000 | [diff] [blame] | 477 | #elif defined(CONFIG_MX53) |
| 478 | } bank[5]; |
| 479 | #endif |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 480 | }; |
| 481 | |
Fabio Estevam | 8b3533c | 2012-05-08 03:40:49 +0000 | [diff] [blame] | 482 | struct fuse_bank0_regs { |
Benoît Thébaudeau | b29e396 | 2013-04-23 10:17:39 +0000 | [diff] [blame] | 483 | u32 fuse0_7[8]; |
| 484 | u32 uid[8]; |
| 485 | u32 fuse16_23[8]; |
| 486 | #if defined(CONFIG_MX51) |
| 487 | u32 imei[8]; |
| 488 | #elif defined(CONFIG_MX53) |
Fabio Estevam | 8b3533c | 2012-05-08 03:40:49 +0000 | [diff] [blame] | 489 | u32 gp[8]; |
Benoît Thébaudeau | b29e396 | 2013-04-23 10:17:39 +0000 | [diff] [blame] | 490 | #endif |
Fabio Estevam | 8b3533c | 2012-05-08 03:40:49 +0000 | [diff] [blame] | 491 | }; |
| 492 | |
Liu Hui-R64343 | 4df6619 | 2010-11-18 23:45:55 +0000 | [diff] [blame] | 493 | struct fuse_bank1_regs { |
| 494 | u32 fuse0_8[9]; |
| 495 | u32 mac_addr[6]; |
| 496 | u32 fuse15_31[0x11]; |
| 497 | }; |
| 498 | |
Benoît Thébaudeau | b29e396 | 2013-04-23 10:17:39 +0000 | [diff] [blame] | 499 | #if defined(CONFIG_MX53) |
| 500 | struct fuse_bank4_regs { |
| 501 | u32 fuse0_4[5]; |
| 502 | u32 gp[3]; |
| 503 | u32 fuse8_31[0x18]; |
| 504 | }; |
| 505 | #endif |
| 506 | |
Martyn Welch | a87af13 | 2017-11-08 15:35:11 +0000 | [diff] [blame] | 507 | #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) |
| 508 | #define PWMCR_DOZEEN (1 << 24) |
| 509 | #define PWMCR_WAITEN (1 << 23) |
| 510 | #define PWMCR_DBGEN (1 << 22) |
| 511 | #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) |
| 512 | #define PWMCR_CLKSRC_IPG (1 << 16) |
| 513 | #define PWMCR_EN (1 << 0) |
| 514 | |
| 515 | struct pwm_regs { |
| 516 | u32 cr; |
| 517 | u32 sr; |
| 518 | u32 ir; |
| 519 | u32 sar; |
| 520 | u32 pr; |
| 521 | u32 cnr; |
| 522 | }; |
| 523 | |
Simon Glass | 559f1a8 | 2020-05-10 11:40:12 -0600 | [diff] [blame] | 524 | #endif /* __ASSEMBLY__ */ |
Stefano Babic | afef6db | 2010-01-20 18:19:51 +0100 | [diff] [blame] | 525 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 526 | #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ |