| Alex Nemirovsky | 1ecad07 | 2020-01-30 12:34:59 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Cortina Access Inc. |
| 4 | * |
| 5 | * Configuration for Cortina-Access Presidio board. |
| 6 | */ |
| 7 | |
| 8 | #ifndef __PRESIDIO_ASIC_H |
| 9 | #define __PRESIDIO_ASIC_H |
| 10 | |
| 11 | #define CONFIG_REMAKE_ELF |
| 12 | |
| 13 | #define CONFIG_SUPPORT_RAW_INITRD |
| 14 | |
| 15 | #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 |
| 16 | #define CONFIG_SYS_BOOTM_LEN 0x00c00000 |
| 17 | |
| 18 | /* Generic Timer Definitions */ |
| 19 | #define COUNTER_FREQUENCY 25000000 |
| 20 | #define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY |
| 21 | #define CONFIG_SYS_TIMER_COUNTER 0xf4321008 |
| 22 | |
| 23 | /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE |
| 24 | * does not yet support DT. Thus define it here. |
| 25 | */ |
| 26 | #define CONFIG_GICV2 |
| 27 | #define GICD_BASE 0xf7011000 |
| 28 | #define GICC_BASE 0xf7012000 |
| 29 | |
| 30 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000 |
| 31 | #define CONFIG_SYS_MEMTEST_START 0x05000000 |
| 32 | #define CONFIG_SYS_MEMTEST_END 0x0D000000 |
| 33 | |
| 34 | /* Size of malloc() pool */ |
| 35 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) |
| 36 | |
| 37 | #define CONFIG_SYS_TIMER_BASE 0xf4321000 |
| 38 | |
| 39 | /* Use external clock source */ |
| 40 | #define PRESIDIO_APB_CLK 125000000 |
| 41 | #define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK |
| 42 | |
| 43 | /* Cortina Serial Configuration */ |
| 44 | #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) |
| 45 | #define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ |
| 46 | (void *)CONFIG_SYS_SERIAL1} |
| 47 | |
| 48 | #define CONFIG_BAUDRATE 115200 |
| 49 | #define CONFIG_SYS_SERIAL0 PER_UART0_CFG |
| 50 | #define CONFIG_SYS_SERIAL1 PER_UART1_CFG |
| 51 | |
| 52 | /* BOOTP options */ |
| 53 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 54 | |
| 55 | /* Miscellaneous configurable options */ |
| 56 | #define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) |
| 57 | #define CONFIG_LAST_STAGE_INIT |
| 58 | |
| 59 | /* SDRAM Bank #1 */ |
| 60 | #define DDR_BASE 0x00000000 |
| 61 | #define PHYS_SDRAM_1 DDR_BASE |
| 62 | #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ |
| 63 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 64 | |
| 65 | /* Console I/O Buffer Size */ |
| 66 | #define CONFIG_SYS_CBSIZE 256 |
| 67 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 68 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 69 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 70 | |
| 71 | /* max command args */ |
| 72 | #define CONFIG_SYS_MAXARGS 64 |
| 73 | #define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" |
| 74 | |
| 75 | #endif /* __PRESIDIO_ASIC_H */ |