Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 9b3789443c47c84f45bb32cdd6e59e4de3114188 / . / configs / khadas-edge-v-rk3399_defconfig
blob: 4b41454d710da4f366c81c2aa719f98e1445d36a [file] [log] [blame]
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]5CONFIG_NR_DRAM_BANKS=1
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]6CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]8CONFIG_ROCKCHIP_RK3399=y
Kever Yang1b662092020-02-19 17:51:07 +0800[diff] [blame]9CONFIG_TARGET_EVB_RK3399=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]10CONFIG_DEBUG_UART_BASE=0xFF1A0000
11CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]12CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]13CONFIG_DEBUG_UART=y
Jared Baldridge0db396b2020-02-06 19:53:14 -0800[diff] [blame]14CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
Tom Rini914a8c02024-01-03 09:26:16 -0500[diff] [blame]15CONFIG_SYS_PBSIZE=1048
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]16CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]17CONFIG_SPL_MAX_SIZE=0x2e000
18CONFIG_SPL_PAD_TO=0x7f8000
Kever Yang20673542019-08-20 11:47:02 +0800[diff] [blame]19# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Quentin Schulz95edee72023-06-21 18:02:52 +0200[diff] [blame]20CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]21CONFIG_TPL=y
Tom Rinic4359852023-10-02 10:35:27 -0400[diff] [blame]22CONFIG_SYS_PROMPT="kedge# "
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]23CONFIG_CMD_BOOTZ=y
24CONFIG_CMD_GPT=y
25CONFIG_CMD_MMC=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]26CONFIG_CMD_USB=y
27# CONFIG_CMD_SETEXPR is not set
28CONFIG_CMD_TIME=y
29CONFIG_SPL_OF_CONTROL=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]30CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
31CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]32CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]33CONFIG_NET_RANDOM_ETHADDR=y
34CONFIG_ROCKCHIP_GPIO=y
35CONFIG_SYS_I2C_ROCKCHIP=y
36CONFIG_MMC_DW=y
37CONFIG_MMC_DW_ROCKCHIP=y
38CONFIG_MMC_SDHCI=y
39CONFIG_MMC_SDHCI_ROCKCHIP=y
40CONFIG_PHY_REALTEK=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]41CONFIG_ETH_DESIGNWARE=y
42CONFIG_GMAC_ROCKCHIP=y
43CONFIG_PMIC_RK8XX=y
44CONFIG_REGULATOR_PWM=y
45CONFIG_REGULATOR_RK8XX=y
46CONFIG_PWM_ROCKCHIP=y
Jagan Teki2da26d72022-12-14 23:20:48 +0530[diff] [blame]47CONFIG_RAM_ROCKCHIP_LPDDR4=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]48CONFIG_BAUDRATE=1500000
49CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]50CONFIG_SYS_NS16550_MEM32=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]51CONFIG_SYSRESET=y
52CONFIG_USB=y
53CONFIG_USB_XHCI_HCD=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]54CONFIG_USB_EHCI_HCD=y
55CONFIG_USB_EHCI_GENERIC=y
Artem Lapkin3227ecb2021-06-07 11:45:05 +0800[diff] [blame]56CONFIG_USB_OHCI_HCD=y
57CONFIG_USB_OHCI_GENERIC=y
Jonas Karlmanac8d1572023-11-12 17:48:57 +0000[diff] [blame]58CONFIG_USB_DWC3=y
59CONFIG_USB_DWC3_GENERIC=y
Nick Xiec142d9a2019-07-30 11:51:15 +0800[diff] [blame]60CONFIG_USB_HOST_ETHER=y
61CONFIG_USB_ETHER_ASIX=y
62CONFIG_USB_ETHER_ASIX88179=y
63CONFIG_USB_ETHER_MCS7830=y
64CONFIG_USB_ETHER_RTL8152=y
65CONFIG_USB_ETHER_SMSC95XX=y
66CONFIG_SPL_TINY_MEMSET=y
67CONFIG_ERRNO_STR=y