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git01.mediatek.com / filogic / uboot / 9ae964b6e64261a3bacda5545c9005cb04967f42 / . / drivers / phy / phy-core-mipi-dphy.c
blob: bb61816add27da42668b399c7b03011040faabea [file] [log] [blame]
Neil Armstrong466fa152020-12-29 14:58:58 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 * Copyright (C) 2018 Cadence Design Systems Inc.
5 */
6
7#include <common.h>
8#include <div64.h>
Igor Prusovc3421ea2023-11-09 20:10:04 +0300[diff] [blame]9#include <linux/time.h>
Neil Armstrong466fa152020-12-29 14:58:58 +0100[diff] [blame]10
11#include <phy-mipi-dphy.h>
12
Neil Armstrong466fa152020-12-29 14:58:58 +0100[diff] [blame]13/*
14 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
15 * from the valid ranges specified in Section 6.9, Table 14, Page 41
16 * of the D-PHY specification (v2.1).
17 */
18int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
19 unsigned int bpp,
20 unsigned int lanes,
21 struct phy_configure_opts_mipi_dphy *cfg)
22{
23 unsigned long long hs_clk_rate;
24 unsigned long long ui;
25
26 if (!cfg)
27 return -EINVAL;
28
29 hs_clk_rate = pixel_clock * bpp;
30 do_div(hs_clk_rate, lanes);
31
32 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
33 do_div(ui, hs_clk_rate);
34
35 cfg->clk_miss = 0;
36 cfg->clk_post = 60000 + 52 * ui;
37 cfg->clk_pre = 8000;
38 cfg->clk_prepare = 38000;
39 cfg->clk_settle = 95000;
40 cfg->clk_term_en = 0;
41 cfg->clk_trail = 60000;
42 cfg->clk_zero = 262000;
43 cfg->d_term_en = 0;
44 cfg->eot = 0;
45 cfg->hs_exit = 100000;
46 cfg->hs_prepare = 40000 + 4 * ui;
47 cfg->hs_zero = 105000 + 6 * ui;
48 cfg->hs_settle = 85000 + 6 * ui;
49 cfg->hs_skip = 40000;
50
51 /*
52 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
53 * contains this formula as:
54 *
55 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
56 *
57 * where n = 1 for forward-direction HS mode and n = 4 for reverse-
58 * direction HS mode. There's only one setting and this function does
59 * not parameterize on anything other that ui, so this code will
60 * assumes that reverse-direction HS mode is supported and uses n = 4.
61 */
62 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
63
64 cfg->init = 100;
65 cfg->lpx = 60000;
66 cfg->ta_get = 5 * cfg->lpx;
67 cfg->ta_go = 4 * cfg->lpx;
68 cfg->ta_sure = 2 * cfg->lpx;
69 cfg->wakeup = 1000;
70
71 cfg->hs_clk_rate = hs_clk_rate;
72 cfg->lanes = lanes;
73
74 return 0;
75}
76
77/*
78 * Validate D-PHY configuration according to MIPI D-PHY specification
79 * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
80 */
81int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
82{
83 unsigned long long ui;
84
85 if (!cfg)
86 return -EINVAL;
87
88 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
89 do_div(ui, cfg->hs_clk_rate);
90
91 if (cfg->clk_miss > 60000)
92 return -EINVAL;
93
94 if (cfg->clk_post < (60000 + 52 * ui))
95 return -EINVAL;
96
97 if (cfg->clk_pre < 8000)
98 return -EINVAL;
99
100 if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
101 return -EINVAL;
102
103 if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
104 return -EINVAL;
105
106 if (cfg->clk_term_en > 38000)
107 return -EINVAL;
108
109 if (cfg->clk_trail < 60000)
110 return -EINVAL;
111
112 if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
113 return -EINVAL;
114
115 if (cfg->d_term_en > (35000 + 4 * ui))
116 return -EINVAL;
117
118 if (cfg->eot > (105000 + 12 * ui))
119 return -EINVAL;
120
121 if (cfg->hs_exit < 100000)
122 return -EINVAL;
123
124 if (cfg->hs_prepare < (40000 + 4 * ui) ||
125 cfg->hs_prepare > (85000 + 6 * ui))
126 return -EINVAL;
127
128 if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
129 return -EINVAL;
130
131 if ((cfg->hs_settle < (85000 + 6 * ui)) ||
132 (cfg->hs_settle > (145000 + 10 * ui)))
133 return -EINVAL;
134
135 if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
136 return -EINVAL;
137
138 if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
139 return -EINVAL;
140
141 if (cfg->init < 100)
142 return -EINVAL;
143
144 if (cfg->lpx < 50000)
145 return -EINVAL;
146
147 if (cfg->ta_get != (5 * cfg->lpx))
148 return -EINVAL;
149
150 if (cfg->ta_go != (4 * cfg->lpx))
151 return -EINVAL;
152
153 if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
154 return -EINVAL;
155
156 if (cfg->wakeup < 1000)
157 return -EINVAL;
158
159 return 0;
160}