blob: 215bcbbef80419a0c92b1ff828b68147d897f742 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Ted Chen9b6dbd42016-01-20 14:24:52 +08002/*
3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
4 *
Stefan Roese47c50972016-06-29 07:58:05 +02005 */
Ted Chen9b6dbd42016-01-20 14:24:52 +08006
7#include <common.h>
Stefan Roese47c50972016-06-29 07:58:05 +02008#include <dm.h>
Ted Chen9b6dbd42016-01-20 14:24:52 +08009#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Ted Chen9b6dbd42016-01-20 14:24:52 +080011#include <malloc.h>
Stefan Roese01094402016-11-22 16:14:23 +010012#include <memalign.h>
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <net.h>
Ted Chen9b6dbd42016-01-20 14:24:52 +080014#include <usb.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
Ted Chen9b6dbd42016-01-20 14:24:52 +080016#include <linux/mii.h>
17#include <linux/bitops.h>
18#include "usb_ether.h"
19#include "r8152.h"
20
Stefan Roese47c50972016-06-29 07:58:05 +020021#ifndef CONFIG_DM_ETH
Ted Chen9b6dbd42016-01-20 14:24:52 +080022/* local vars */
23static int curr_eth_dev; /* index for name of next device detected */
24
25struct r8152_dongle {
26 unsigned short vendor;
27 unsigned short product;
28};
29
Philipp Tomsich657bc532017-06-25 22:47:15 +020030static const struct r8152_dongle r8152_dongles[] = {
Ted Chen9b6dbd42016-01-20 14:24:52 +080031 /* Realtek */
32 { 0x0bda, 0x8050 },
33 { 0x0bda, 0x8152 },
34 { 0x0bda, 0x8153 },
35
36 /* Samsung */
37 { 0x04e8, 0xa101 },
38
39 /* Lenovo */
40 { 0x17ef, 0x304f },
41 { 0x17ef, 0x3052 },
42 { 0x17ef, 0x3054 },
43 { 0x17ef, 0x3057 },
44 { 0x17ef, 0x7205 },
45 { 0x17ef, 0x720a },
46 { 0x17ef, 0x720b },
47 { 0x17ef, 0x720c },
48
49 /* TP-LINK */
50 { 0x2357, 0x0601 },
51
52 /* Nvidia */
53 { 0x0955, 0x09ff },
54};
Stefan Roese47c50972016-06-29 07:58:05 +020055#endif
56
57struct r8152_version {
58 unsigned short tcr;
59 unsigned short version;
60 bool gmii;
61};
Ted Chen9b6dbd42016-01-20 14:24:52 +080062
Philipp Tomsich657bc532017-06-25 22:47:15 +020063static const struct r8152_version r8152_versions[] = {
Ted Chen9b6dbd42016-01-20 14:24:52 +080064 { 0x4c00, RTL_VER_01, 0 },
65 { 0x4c10, RTL_VER_02, 0 },
66 { 0x5c00, RTL_VER_03, 1 },
67 { 0x5c10, RTL_VER_04, 1 },
68 { 0x5c20, RTL_VER_05, 1 },
69 { 0x5c30, RTL_VER_06, 1 },
70 { 0x4800, RTL_VER_07, 0 },
Hayes Wangd215ca22020-06-16 17:09:47 +080071 { 0x6000, RTL_VER_08, 1 },
72 { 0x6010, RTL_VER_09, 1 },
Ted Chen9b6dbd42016-01-20 14:24:52 +080073};
74
75static
76int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
77{
Stefan Roese01094402016-11-22 16:14:23 +010078 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
79 int ret;
80
81 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
82 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
83 value, index, tmp, size, 500);
84 memcpy(data, tmp, size);
85 return ret;
Ted Chen9b6dbd42016-01-20 14:24:52 +080086}
87
88static
89int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
90{
Stefan Roese01094402016-11-22 16:14:23 +010091 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
92
93 memcpy(tmp, data, size);
Ted Chen9b6dbd42016-01-20 14:24:52 +080094 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
95 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
Stefan Roese01094402016-11-22 16:14:23 +010096 value, index, tmp, size, 500);
Ted Chen9b6dbd42016-01-20 14:24:52 +080097}
98
99int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
100 void *data, u16 type)
101{
102 u16 burst_size = 64;
103 int ret;
104 int txsize;
105
106 /* both size and index must be 4 bytes align */
107 if ((size & 3) || !size || (index & 3) || !data)
108 return -EINVAL;
109
110 if (index + size > 0xffff)
111 return -EINVAL;
112
113 while (size) {
114 txsize = min(size, burst_size);
115 ret = get_registers(tp, index, type, txsize, data);
116 if (ret < 0)
117 break;
118
119 index += txsize;
120 data += txsize;
121 size -= txsize;
122 }
123
124 return ret;
125}
126
127int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
128 u16 size, void *data, u16 type)
129{
130 int ret;
131 u16 byteen_start, byteen_end, byte_en_to_hw;
132 u16 burst_size = 512;
133 int txsize;
134
135 /* both size and index must be 4 bytes align */
136 if ((size & 3) || !size || (index & 3) || !data)
137 return -EINVAL;
138
139 if (index + size > 0xffff)
140 return -EINVAL;
141
142 byteen_start = byteen & BYTE_EN_START_MASK;
143 byteen_end = byteen & BYTE_EN_END_MASK;
144
145 byte_en_to_hw = byteen_start | (byteen_start << 4);
146 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
147 if (ret < 0)
148 return ret;
149
150 index += 4;
151 data += 4;
152 size -= 4;
153
154 if (size) {
155 size -= 4;
156
157 while (size) {
158 txsize = min(size, burst_size);
159
160 ret = set_registers(tp, index,
161 type | BYTE_EN_DWORD,
162 txsize, data);
163 if (ret < 0)
164 return ret;
165
166 index += txsize;
167 data += txsize;
168 size -= txsize;
169 }
170
171 byte_en_to_hw = byteen_end | (byteen_end >> 4);
172 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
173 if (ret < 0)
174 return ret;
175 }
176
177 return ret;
178}
179
180int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
181{
182 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
183}
184
185int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
186{
187 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
188}
189
190int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
191{
192 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
193}
194
195int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
196{
197 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
198}
199
200u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
201{
202 __le32 data;
203
204 generic_ocp_read(tp, index, sizeof(data), &data, type);
205
206 return __le32_to_cpu(data);
207}
208
209void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
210{
211 __le32 tmp = __cpu_to_le32(data);
212
213 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
214}
215
216u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
217{
218 u32 data;
219 __le32 tmp;
220 u8 shift = index & 2;
221
222 index &= ~3;
223
224 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
225
226 data = __le32_to_cpu(tmp);
227 data >>= (shift * 8);
228 data &= 0xffff;
229
230 return data;
231}
232
233void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
234{
235 u32 mask = 0xffff;
236 __le32 tmp;
237 u16 byen = BYTE_EN_WORD;
238 u8 shift = index & 2;
239
240 data &= mask;
241
242 if (index & 2) {
243 byen <<= shift;
244 mask <<= (shift * 8);
245 data <<= (shift * 8);
246 index &= ~3;
247 }
248
249 tmp = __cpu_to_le32(data);
250
251 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
252}
253
254u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
255{
256 u32 data;
257 __le32 tmp;
258 u8 shift = index & 3;
259
260 index &= ~3;
261
262 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
263
264 data = __le32_to_cpu(tmp);
265 data >>= (shift * 8);
266 data &= 0xff;
267
268 return data;
269}
270
271void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
272{
273 u32 mask = 0xff;
274 __le32 tmp;
275 u16 byen = BYTE_EN_BYTE;
276 u8 shift = index & 3;
277
278 data &= mask;
279
280 if (index & 3) {
281 byen <<= shift;
282 mask <<= (shift * 8);
283 data <<= (shift * 8);
284 index &= ~3;
285 }
286
287 tmp = __cpu_to_le32(data);
288
289 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
290}
291
292u16 ocp_reg_read(struct r8152 *tp, u16 addr)
293{
294 u16 ocp_base, ocp_index;
295
296 ocp_base = addr & 0xf000;
297 if (ocp_base != tp->ocp_base) {
298 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
299 tp->ocp_base = ocp_base;
300 }
301
302 ocp_index = (addr & 0x0fff) | 0xb000;
303 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
304}
305
306void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
307{
308 u16 ocp_base, ocp_index;
309
310 ocp_base = addr & 0xf000;
311 if (ocp_base != tp->ocp_base) {
312 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
313 tp->ocp_base = ocp_base;
314 }
315
316 ocp_index = (addr & 0x0fff) | 0xb000;
317 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
318}
319
320static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
321{
322 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
323}
324
325static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
326{
327 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
328}
329
330void sram_write(struct r8152 *tp, u16 addr, u16 data)
331{
332 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
333 ocp_reg_write(tp, OCP_SRAM_DATA, data);
334}
335
Hayes Wangd215ca22020-06-16 17:09:47 +0800336static u16 sram_read(struct r8152 *tp, u16 addr)
337{
338 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
339 return ocp_reg_read(tp, OCP_SRAM_DATA);
340}
341
Ted Chen9b6dbd42016-01-20 14:24:52 +0800342int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
343 const u32 mask, bool set, unsigned int timeout)
344{
345 u32 val;
346
347 while (--timeout) {
348 if (ocp_reg)
349 val = ocp_reg_read(tp, index);
350 else
351 val = ocp_read_dword(tp, type, index);
352
353 if (!set)
354 val = ~val;
355
356 if ((val & mask) == mask)
357 return 0;
358
359 mdelay(1);
360 }
361
362 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
363 __func__, index, mask, timeout);
364
365 return -ETIMEDOUT;
366}
367
368static void r8152b_reset_packet_filter(struct r8152 *tp)
369{
370 u32 ocp_data;
371
372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
373 ocp_data &= ~FMC_FCR_MCU_EN;
374 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
375 ocp_data |= FMC_FCR_MCU_EN;
376 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
377}
378
379static void rtl8152_wait_fifo_empty(struct r8152 *tp)
380{
381 int ret;
382
383 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
384 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
385 if (ret)
386 debug("Timeout waiting for FIFO empty\n");
387
388 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
389 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
390 if (ret)
391 debug("Timeout waiting for TX empty\n");
392}
393
394static void rtl8152_nic_reset(struct r8152 *tp)
395{
396 int ret;
397 u32 ocp_data;
398
399 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
400 ocp_data |= BIST_CTRL_SW_RESET;
401 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
402
403 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
404 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
405 if (ret)
406 debug("Timeout waiting for NIC reset\n");
407}
408
409static u8 rtl8152_get_speed(struct r8152 *tp)
410{
411 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
412}
413
414static void rtl_set_eee_plus(struct r8152 *tp)
415{
416 u32 ocp_data;
417
418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
419 ocp_data &= ~EEEP_CR_EEEP_TX;
420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
421}
422
423static void rxdy_gated_en(struct r8152 *tp, bool enable)
424{
425 u32 ocp_data;
426
427 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
428 if (enable)
429 ocp_data |= RXDY_GATED_EN;
430 else
431 ocp_data &= ~RXDY_GATED_EN;
432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
433}
434
435static void rtl8152_set_rx_mode(struct r8152 *tp)
436{
437 u32 ocp_data;
438 __le32 tmp[2];
439
440 tmp[0] = 0xffffffff;
441 tmp[1] = 0xffffffff;
442
443 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
444
445 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
446 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
447 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
448}
449
450static int rtl_enable(struct r8152 *tp)
451{
452 u32 ocp_data;
453
454 r8152b_reset_packet_filter(tp);
455
456 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
457 ocp_data |= PLA_CR_RE | PLA_CR_TE;
458 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
459
460 rxdy_gated_en(tp, false);
461
462 rtl8152_set_rx_mode(tp);
463
464 return 0;
465}
466
467static int rtl8152_enable(struct r8152 *tp)
468{
469 rtl_set_eee_plus(tp);
470
471 return rtl_enable(tp);
472}
473
474static void r8153_set_rx_early_timeout(struct r8152 *tp)
475{
476 u32 ocp_data = tp->coalesce / 8;
477
Hayes Wangd215ca22020-06-16 17:09:47 +0800478 switch (tp->version) {
479 case RTL_VER_03:
480 case RTL_VER_04:
481 case RTL_VER_05:
482 case RTL_VER_06:
483 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
484 ocp_data);
485 break;
486
487 case RTL_VER_08:
488 case RTL_VER_09:
489 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
490 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 1264ns.
491 */
492 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
493 RX_AUXILIARY_TIMER / 8);
494 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
495 ocp_data);
496 break;
497
498 default:
499 debug("** %s Invalid Device\n", __func__);
500 break;
501 }
Ted Chen9b6dbd42016-01-20 14:24:52 +0800502}
503
504static void r8153_set_rx_early_size(struct r8152 *tp)
505{
Hayes Wangd215ca22020-06-16 17:09:47 +0800506 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS -
507 sizeof(struct rx_desc));
508
509 switch (tp->version) {
510 case RTL_VER_03:
511 case RTL_VER_04:
512 case RTL_VER_05:
513 case RTL_VER_06:
514 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
515 ocp_data / 4);
516 break;
517
518 case RTL_VER_08:
519 case RTL_VER_09:
520 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
521 ocp_data / 8);
522 break;
523
524 default:
525 debug("** %s Invalid Device\n", __func__);
526 break;
527 }
Ted Chen9b6dbd42016-01-20 14:24:52 +0800528
529 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
530}
531
532static int rtl8153_enable(struct r8152 *tp)
533{
534 rtl_set_eee_plus(tp);
535 r8153_set_rx_early_timeout(tp);
536 r8153_set_rx_early_size(tp);
537
538 return rtl_enable(tp);
539}
540
541static void rtl_disable(struct r8152 *tp)
542{
543 u32 ocp_data;
544
545 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
546 ocp_data &= ~RCR_ACPT_ALL;
547 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
548
549 rxdy_gated_en(tp, true);
550
551 rtl8152_wait_fifo_empty(tp);
552 rtl8152_nic_reset(tp);
553}
554
555static void r8152_power_cut_en(struct r8152 *tp, bool enable)
556{
557 u32 ocp_data;
558
559 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
560 if (enable)
561 ocp_data |= POWER_CUT;
562 else
563 ocp_data &= ~POWER_CUT;
564 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
565
566 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
567 ocp_data &= ~RESUME_INDICATE;
568 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
569}
570
571static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
572{
573 u32 ocp_data;
574
575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
576 if (enable)
577 ocp_data |= CPCR_RX_VLAN;
578 else
579 ocp_data &= ~CPCR_RX_VLAN;
580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
581}
582
583static void r8153_u1u2en(struct r8152 *tp, bool enable)
584{
585 u8 u1u2[8];
586
587 if (enable)
588 memset(u1u2, 0xff, sizeof(u1u2));
589 else
590 memset(u1u2, 0x00, sizeof(u1u2));
591
592 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
593}
594
Hayes Wangd215ca22020-06-16 17:09:47 +0800595static void r8153b_u1u2en(struct r8152 *tp, bool enable)
596{
597 u16 ocp_data;
598
599 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
600 if (enable)
601 ocp_data |= LPM_U1U2_EN;
602 else
603 ocp_data &= ~LPM_U1U2_EN;
604
605 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
606}
607
Ted Chen9b6dbd42016-01-20 14:24:52 +0800608static void r8153_u2p3en(struct r8152 *tp, bool enable)
609{
610 u32 ocp_data;
611
612 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
613 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
614 ocp_data |= U2P3_ENABLE;
615 else
616 ocp_data &= ~U2P3_ENABLE;
617 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
618}
619
620static void r8153_power_cut_en(struct r8152 *tp, bool enable)
621{
622 u32 ocp_data;
623
624 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
625 if (enable)
626 ocp_data |= PWR_EN | PHASE2_EN;
627 else
628 ocp_data &= ~(PWR_EN | PHASE2_EN);
629 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
630
631 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
632 ocp_data &= ~PCUT_STATUS;
633 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
634}
635
Hayes Wang653d2e72020-06-16 17:09:44 +0800636static void rtl_reset_bmu(struct r8152 *tp)
637{
638 u8 ocp_data;
639
640 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
641 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
642 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
643 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
644 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
645}
646
Ted Chen9b6dbd42016-01-20 14:24:52 +0800647static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
648{
649 int ret;
650 unsigned char enetaddr[8] = {0};
651
652 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
653 if (ret < 0)
654 return ret;
655
656 memcpy(macaddr, enetaddr, ETH_ALEN);
657 return 0;
658}
659
660static void r8152b_disable_aldps(struct r8152 *tp)
661{
662 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
663 mdelay(20);
664}
665
666static void r8152b_enable_aldps(struct r8152 *tp)
667{
668 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
669 LINKENA | DIS_SDSAVE);
670}
671
672static void rtl8152_disable(struct r8152 *tp)
673{
674 r8152b_disable_aldps(tp);
675 rtl_disable(tp);
676 r8152b_enable_aldps(tp);
677}
678
679static void r8152b_hw_phy_cfg(struct r8152 *tp)
680{
681 u16 data;
682
683 data = r8152_mdio_read(tp, MII_BMCR);
684 if (data & BMCR_PDOWN) {
685 data &= ~BMCR_PDOWN;
686 r8152_mdio_write(tp, MII_BMCR, data);
687 }
688
689 r8152b_firmware(tp);
690}
691
692static void rtl8152_reinit_ll(struct r8152 *tp)
693{
694 u32 ocp_data;
695 int ret;
696
697 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
698 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
699 if (ret)
700 debug("Timeout waiting for link list ready\n");
701
702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
703 ocp_data |= RE_INIT_LL;
704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
705
706 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
707 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
708 if (ret)
709 debug("Timeout waiting for link list ready\n");
710}
711
712static void r8152b_exit_oob(struct r8152 *tp)
713{
714 u32 ocp_data;
715
716 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
717 ocp_data &= ~RCR_ACPT_ALL;
718 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
719
720 rxdy_gated_en(tp, true);
721 r8152b_hw_phy_cfg(tp);
722
723 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
724 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
725
726 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
727 ocp_data &= ~NOW_IS_OOB;
728 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
729
730 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
731 ocp_data &= ~MCU_BORW_EN;
732 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
733
734 rtl8152_reinit_ll(tp);
735 rtl8152_nic_reset(tp);
736
737 /* rx share fifo credit full threshold */
738 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
739
740 if (tp->udev->speed == USB_SPEED_FULL ||
741 tp->udev->speed == USB_SPEED_LOW) {
742 /* rx share fifo credit near full threshold */
743 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
744 RXFIFO_THR2_FULL);
745 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
746 RXFIFO_THR3_FULL);
747 } else {
748 /* rx share fifo credit near full threshold */
749 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
750 RXFIFO_THR2_HIGH);
751 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
752 RXFIFO_THR3_HIGH);
753 }
754
755 /* TX share fifo free credit full threshold */
756 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
757
758 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
759 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
760 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
761 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
762
763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
764
765 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
766 ocp_data |= TCR0_AUTO_FIFO;
767 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
768}
769
770static void r8152b_enter_oob(struct r8152 *tp)
771{
772 u32 ocp_data;
773
774 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
775 ocp_data &= ~NOW_IS_OOB;
776 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
777
778 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
779 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
780 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
781
782 rtl_disable(tp);
783
784 rtl8152_reinit_ll(tp);
785
786 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
787
788 rtl_rx_vlan_en(tp, false);
789
Hayes Wang1bb3ee42020-05-22 16:54:11 +0800790 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
Ted Chen9b6dbd42016-01-20 14:24:52 +0800791 ocp_data |= ALDPS_PROXY_MODE;
Hayes Wang1bb3ee42020-05-22 16:54:11 +0800792 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
Ted Chen9b6dbd42016-01-20 14:24:52 +0800793
794 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
795 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
796 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
797
798 rxdy_gated_en(tp, false);
799
800 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
801 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
802 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
803}
804
805static void r8153_hw_phy_cfg(struct r8152 *tp)
806{
807 u32 ocp_data;
808 u16 data;
809
810 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
811 tp->version == RTL_VER_05)
812 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
813
814 data = r8152_mdio_read(tp, MII_BMCR);
815 if (data & BMCR_PDOWN) {
816 data &= ~BMCR_PDOWN;
817 r8152_mdio_write(tp, MII_BMCR, data);
818 }
819
820 r8153_firmware(tp);
821
822 if (tp->version == RTL_VER_03) {
823 data = ocp_reg_read(tp, OCP_EEE_CFG);
824 data &= ~CTAP_SHORT_EN;
825 ocp_reg_write(tp, OCP_EEE_CFG, data);
826 }
827
828 data = ocp_reg_read(tp, OCP_POWER_CFG);
829 data |= EEE_CLKDIV_EN;
830 ocp_reg_write(tp, OCP_POWER_CFG, data);
831
832 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
833 data |= EN_10M_BGOFF;
834 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
835 data = ocp_reg_read(tp, OCP_POWER_CFG);
836 data |= EN_10M_PLLOFF;
837 ocp_reg_write(tp, OCP_POWER_CFG, data);
838 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
839
840 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
841 ocp_data |= PFM_PWM_SWITCH;
842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
843
844 /* Enable LPF corner auto tune */
845 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
846
847 /* Adjust 10M Amplitude */
848 sram_write(tp, SRAM_10M_AMP1, 0x00af);
849 sram_write(tp, SRAM_10M_AMP2, 0x0208);
850}
851
Hayes Wangd215ca22020-06-16 17:09:47 +0800852static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
853{
854 u32 ocp_data;
855
856 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
857 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
858 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
859 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
860
861 return ocp_data;
862}
863
864static void r8153b_hw_phy_cfg(struct r8152 *tp)
865{
866 u32 ocp_data;
867 u16 data;
868
869 data = r8152_mdio_read(tp, MII_BMCR);
870 if (data & BMCR_PDOWN) {
871 data &= ~BMCR_PDOWN;
872 r8152_mdio_write(tp, MII_BMCR, data);
873 }
874
875 /* U1/U2/L1 idle timer. 500 us */
876 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
877
878 r8153b_firmware(tp);
879
880 data = sram_read(tp, SRAM_GREEN_CFG);
881 data |= R_TUNE_EN;
882 sram_write(tp, SRAM_GREEN_CFG, data);
883 data = ocp_reg_read(tp, OCP_NCTL_CFG);
884 data |= PGA_RETURN_EN;
885 ocp_reg_write(tp, OCP_NCTL_CFG, data);
886
887 /* ADC Bias Calibration:
888 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
889 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
890 * ADC ioffset.
891 */
892 ocp_data = r8152_efuse_read(tp, 0x7d);
893 ocp_data = ((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7);
894 if (ocp_data != 0xffff)
895 ocp_reg_write(tp, OCP_ADC_IOFFSET, ocp_data);
896
897 /* ups mode tx-link-pulse timing adjustment:
898 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
899 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
900 */
901 ocp_data = ocp_reg_read(tp, 0xc426);
902 ocp_data &= 0x3fff;
903 if (ocp_data) {
904 u32 swr_cnt_1ms_ini;
905
906 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
907 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
908 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
909 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
910 }
911
912 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
913 ocp_data |= PFM_PWM_SWITCH;
914 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
915}
916
Ted Chen9b6dbd42016-01-20 14:24:52 +0800917static void r8153_first_init(struct r8152 *tp)
918{
919 u32 ocp_data;
920
921 rxdy_gated_en(tp, true);
922
923 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
924 ocp_data &= ~RCR_ACPT_ALL;
925 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
926
927 r8153_hw_phy_cfg(tp);
928
929 rtl8152_nic_reset(tp);
Hayes Wang653d2e72020-06-16 17:09:44 +0800930 rtl_reset_bmu(tp);
Ted Chen9b6dbd42016-01-20 14:24:52 +0800931
932 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
933 ocp_data &= ~NOW_IS_OOB;
934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
935
936 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
937 ocp_data &= ~MCU_BORW_EN;
938 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
939
940 rtl8152_reinit_ll(tp);
941
942 rtl_rx_vlan_en(tp, false);
943
944 ocp_data = RTL8153_RMS;
945 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
946 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
947
948 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
949 ocp_data |= TCR0_AUTO_FIFO;
950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
951
952 rtl8152_nic_reset(tp);
953
954 /* rx share fifo credit full threshold */
955 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
957 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
958 /* TX share fifo free credit full threshold */
959 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
960
961 /* rx aggregation */
962 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
963
964 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
965 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
966}
967
968static void r8153_enter_oob(struct r8152 *tp)
969{
970 u32 ocp_data;
971
972 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
973 ocp_data &= ~NOW_IS_OOB;
974 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
975
976 rtl_disable(tp);
Hayes Wang653d2e72020-06-16 17:09:44 +0800977 rtl_reset_bmu(tp);
Ted Chen9b6dbd42016-01-20 14:24:52 +0800978
979 rtl8152_reinit_ll(tp);
980
981 ocp_data = RTL8153_RMS;
982 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
983
984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
985 ocp_data &= ~TEREDO_WAKE_MASK;
986 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
987
988 rtl_rx_vlan_en(tp, false);
989
Hayes Wang1bb3ee42020-05-22 16:54:11 +0800990 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
Ted Chen9b6dbd42016-01-20 14:24:52 +0800991 ocp_data |= ALDPS_PROXY_MODE;
Hayes Wang1bb3ee42020-05-22 16:54:11 +0800992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
Ted Chen9b6dbd42016-01-20 14:24:52 +0800993
994 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
995 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
996 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
997
998 rxdy_gated_en(tp, false);
999
1000 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1001 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1002 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1003}
1004
1005static void r8153_disable_aldps(struct r8152 *tp)
1006{
1007 u16 data;
1008
1009 data = ocp_reg_read(tp, OCP_POWER_CFG);
1010 data &= ~EN_ALDPS;
1011 ocp_reg_write(tp, OCP_POWER_CFG, data);
1012 mdelay(20);
1013}
1014
1015static void rtl8153_disable(struct r8152 *tp)
1016{
1017 r8153_disable_aldps(tp);
1018 rtl_disable(tp);
Hayes Wang653d2e72020-06-16 17:09:44 +08001019 rtl_reset_bmu(tp);
Ted Chen9b6dbd42016-01-20 14:24:52 +08001020}
1021
1022static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1023{
1024 u16 bmcr, anar, gbcr;
1025
1026 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1027 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1028 ADVERTISE_100HALF | ADVERTISE_100FULL);
1029 if (tp->supports_gmii) {
1030 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
1031 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1032 } else {
1033 gbcr = 0;
1034 }
1035
1036 if (autoneg == AUTONEG_DISABLE) {
1037 if (speed == SPEED_10) {
1038 bmcr = 0;
1039 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1040 } else if (speed == SPEED_100) {
1041 bmcr = BMCR_SPEED100;
1042 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1043 } else if (speed == SPEED_1000 && tp->supports_gmii) {
1044 bmcr = BMCR_SPEED1000;
1045 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1046 } else {
1047 return -EINVAL;
1048 }
1049
1050 if (duplex == DUPLEX_FULL)
1051 bmcr |= BMCR_FULLDPLX;
1052 } else {
1053 if (speed == SPEED_10) {
1054 if (duplex == DUPLEX_FULL)
1055 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1056 else
1057 anar |= ADVERTISE_10HALF;
1058 } else if (speed == SPEED_100) {
1059 if (duplex == DUPLEX_FULL) {
1060 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1061 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1062 } else {
1063 anar |= ADVERTISE_10HALF;
1064 anar |= ADVERTISE_100HALF;
1065 }
1066 } else if (speed == SPEED_1000 && tp->supports_gmii) {
1067 if (duplex == DUPLEX_FULL) {
1068 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1069 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1070 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1071 } else {
1072 anar |= ADVERTISE_10HALF;
1073 anar |= ADVERTISE_100HALF;
1074 gbcr |= ADVERTISE_1000HALF;
1075 }
1076 } else {
1077 return -EINVAL;
1078 }
1079
Hayes Wang27217bc2020-06-16 17:09:45 +08001080 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001081 }
1082
1083 if (tp->supports_gmii)
1084 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
1085
1086 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1087 r8152_mdio_write(tp, MII_BMCR, bmcr);
1088
1089 return 0;
1090}
1091
1092static void rtl8152_up(struct r8152 *tp)
1093{
1094 r8152b_disable_aldps(tp);
1095 r8152b_exit_oob(tp);
1096 r8152b_enable_aldps(tp);
1097}
1098
1099static void rtl8152_down(struct r8152 *tp)
1100{
1101 r8152_power_cut_en(tp, false);
1102 r8152b_disable_aldps(tp);
1103 r8152b_enter_oob(tp);
1104 r8152b_enable_aldps(tp);
1105}
1106
1107static void rtl8153_up(struct r8152 *tp)
1108{
1109 r8153_u1u2en(tp, false);
1110 r8153_disable_aldps(tp);
1111 r8153_first_init(tp);
1112 r8153_u2p3en(tp, false);
1113}
1114
1115static void rtl8153_down(struct r8152 *tp)
1116{
1117 r8153_u1u2en(tp, false);
1118 r8153_u2p3en(tp, false);
1119 r8153_power_cut_en(tp, false);
1120 r8153_disable_aldps(tp);
1121 r8153_enter_oob(tp);
1122}
1123
Hayes Wangd215ca22020-06-16 17:09:47 +08001124static void rtl8153b_up(struct r8152 *tp)
1125{
1126 r8153_first_init(tp);
1127}
1128
1129static void rtl8153b_down(struct r8152 *tp)
1130{
1131 r8153_enter_oob(tp);
1132}
1133
Ted Chen9b6dbd42016-01-20 14:24:52 +08001134static void r8152b_get_version(struct r8152 *tp)
1135{
1136 u32 ocp_data;
1137 u16 tcr;
1138 int i;
1139
1140 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
1141 tcr = (u16)(ocp_data & VERSION_MASK);
1142
1143 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
1144 if (tcr == r8152_versions[i].tcr) {
1145 /* Found a supported version */
1146 tp->version = r8152_versions[i].version;
1147 tp->supports_gmii = r8152_versions[i].gmii;
1148 break;
1149 }
1150 }
1151
1152 if (tp->version == RTL_VER_UNKNOWN)
1153 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
1154}
1155
1156static void r8152b_enable_fc(struct r8152 *tp)
1157{
1158 u16 anar;
1159 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1160 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1161 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1162}
1163
1164static void rtl_tally_reset(struct r8152 *tp)
1165{
1166 u32 ocp_data;
1167
1168 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1169 ocp_data |= TALLY_RESET;
1170 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1171}
1172
1173static void r8152b_init(struct r8152 *tp)
1174{
1175 u32 ocp_data;
1176
1177 r8152b_disable_aldps(tp);
1178
1179 if (tp->version == RTL_VER_01) {
1180 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1181 ocp_data &= ~LED_MODE_MASK;
1182 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1183 }
1184
1185 r8152_power_cut_en(tp, false);
1186
1187 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1188 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1190 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1191 ocp_data &= ~MCU_CLK_RATIO_MASK;
1192 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1193 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1194 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1195 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1197
1198 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1199 ocp_data |= BIT(15);
1200 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1201 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1202 ocp_data &= ~BIT(15);
1203 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1204
1205 r8152b_enable_fc(tp);
1206 rtl_tally_reset(tp);
1207
1208 /* enable rx aggregation */
1209 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1210
1211 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1212 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1213}
1214
1215static void r8153_init(struct r8152 *tp)
1216{
1217 int i;
1218 u32 ocp_data;
1219
1220 r8153_disable_aldps(tp);
1221 r8153_u1u2en(tp, false);
1222
1223 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1224 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1225
1226 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1227 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1228 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1229 break;
1230
1231 mdelay(1);
1232 }
1233
1234 r8153_u2p3en(tp, false);
1235
1236 if (tp->version == RTL_VER_04) {
1237 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1238 ocp_data &= ~pwd_dn_scale_mask;
1239 ocp_data |= pwd_dn_scale(96);
1240 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1241
1242 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1243 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1244 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1245 } else if (tp->version == RTL_VER_05) {
1246 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1247 ocp_data &= ~ECM_ALDPS;
1248 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1249
1250 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1251 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1252 ocp_data &= ~DYNAMIC_BURST;
1253 else
1254 ocp_data |= DYNAMIC_BURST;
1255 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1256 } else if (tp->version == RTL_VER_06) {
1257 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1258 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1259 ocp_data &= ~DYNAMIC_BURST;
1260 else
1261 ocp_data |= DYNAMIC_BURST;
1262 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1263 }
1264
1265 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1266 ocp_data |= EP4_FULL_FC;
1267 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1268
1269 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1270 ocp_data &= ~TIMER11_EN;
1271 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1272
1273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1274 ocp_data &= ~LED_MODE_MASK;
1275 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1276
1277 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1278 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1279 ocp_data |= LPM_TIMER_500MS;
1280 else
1281 ocp_data |= LPM_TIMER_500US;
1282 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1283
1284 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1285 ocp_data &= ~SEN_VAL_MASK;
1286 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1287 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1288
1289 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1290
1291 r8153_power_cut_en(tp, false);
1292
1293 r8152b_enable_fc(tp);
1294 rtl_tally_reset(tp);
1295}
1296
Hayes Wangd215ca22020-06-16 17:09:47 +08001297static void r8153b_init(struct r8152 *tp)
1298{
1299 u32 ocp_data;
1300 int i;
1301
1302 r8153_disable_aldps(tp);
1303 r8153b_u1u2en(tp, false);
1304
1305 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1306 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1307
1308 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1309 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1310 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1311 break;
1312
1313 mdelay(1);
1314 }
1315
1316 r8153_u2p3en(tp, false);
1317
1318 /* MSC timer = 0xfff * 8ms = 32760 ms */
1319 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
1320
1321 r8153_power_cut_en(tp, false);
1322
1323 /* MAC clock speed down */
1324 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
1325 ocp_data |= MAC_CLK_SPDWN_EN;
1326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
1327
1328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1329 ocp_data &= ~PLA_MCU_SPDWN_EN;
1330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1331
1332 if (tp->version == RTL_VER_09) {
1333 /* Disable Test IO for 32QFN */
1334 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
1335 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1336 ocp_data |= TEST_IO_OFF;
1337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1338 }
1339 }
1340
1341 /* rx aggregation */
1342 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1343 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1344 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1345
1346 rtl_tally_reset(tp);
1347 r8153b_hw_phy_cfg(tp);
1348 r8152b_enable_fc(tp);
1349}
1350
Ted Chen9b6dbd42016-01-20 14:24:52 +08001351static void rtl8152_unload(struct r8152 *tp)
1352{
1353 if (tp->version != RTL_VER_01)
1354 r8152_power_cut_en(tp, true);
1355}
1356
1357static void rtl8153_unload(struct r8152 *tp)
1358{
1359 r8153_power_cut_en(tp, false);
1360}
1361
1362static int rtl_ops_init(struct r8152 *tp)
1363{
1364 struct rtl_ops *ops = &tp->rtl_ops;
1365 int ret = 0;
1366
1367 switch (tp->version) {
1368 case RTL_VER_01:
1369 case RTL_VER_02:
1370 case RTL_VER_07:
1371 ops->init = r8152b_init;
1372 ops->enable = rtl8152_enable;
1373 ops->disable = rtl8152_disable;
1374 ops->up = rtl8152_up;
1375 ops->down = rtl8152_down;
1376 ops->unload = rtl8152_unload;
1377 break;
1378
1379 case RTL_VER_03:
1380 case RTL_VER_04:
1381 case RTL_VER_05:
1382 case RTL_VER_06:
1383 ops->init = r8153_init;
1384 ops->enable = rtl8153_enable;
1385 ops->disable = rtl8153_disable;
1386 ops->up = rtl8153_up;
1387 ops->down = rtl8153_down;
1388 ops->unload = rtl8153_unload;
1389 break;
1390
Hayes Wangd215ca22020-06-16 17:09:47 +08001391 case RTL_VER_08:
1392 case RTL_VER_09:
1393 ops->init = r8153b_init;
1394 ops->enable = rtl8153_enable;
1395 ops->disable = rtl8153_disable;
1396 ops->up = rtl8153b_up;
1397 ops->down = rtl8153b_down;
1398 break;
1399
Ted Chen9b6dbd42016-01-20 14:24:52 +08001400 default:
1401 ret = -ENODEV;
1402 printf("r8152 Unknown Device\n");
1403 break;
1404 }
1405
1406 return ret;
1407}
1408
Stefan Roese47c50972016-06-29 07:58:05 +02001409static int r8152_init_common(struct r8152 *tp)
Ted Chen9b6dbd42016-01-20 14:24:52 +08001410{
Ted Chen9b6dbd42016-01-20 14:24:52 +08001411 u8 speed;
1412 int timeout = 0;
1413 int link_detected;
1414
1415 debug("** %s()\n", __func__);
1416
1417 do {
1418 speed = rtl8152_get_speed(tp);
1419
1420 link_detected = speed & LINK_STATUS;
1421 if (!link_detected) {
1422 if (timeout == 0)
1423 printf("Waiting for Ethernet connection... ");
1424 mdelay(TIMEOUT_RESOLUTION);
1425 timeout += TIMEOUT_RESOLUTION;
1426 }
1427 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1428 if (link_detected) {
1429 tp->rtl_ops.enable(tp);
1430
1431 if (timeout != 0)
1432 printf("done.\n");
1433 } else {
1434 printf("unable to connect.\n");
1435 }
1436
1437 return 0;
1438}
1439
Stefan Roese47c50972016-06-29 07:58:05 +02001440static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
Ted Chen9b6dbd42016-01-20 14:24:52 +08001441{
Stefan Roese47c50972016-06-29 07:58:05 +02001442 struct usb_device *udev = ueth->pusb_dev;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001443 u32 opts1, opts2 = 0;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001444 int err;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001445 int actual_len;
Stefan Roese01094402016-11-22 16:14:23 +01001446 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
1447 PKTSIZE + sizeof(struct tx_desc));
Ted Chen9b6dbd42016-01-20 14:24:52 +08001448 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1449
1450 debug("** %s(), len %d\n", __func__, length);
1451
1452 opts1 = length | TX_FS | TX_LS;
1453
1454 tx_desc->opts2 = cpu_to_le32(opts2);
1455 tx_desc->opts1 = cpu_to_le32(opts1);
1456
1457 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1458
Stefan Roese47c50972016-06-29 07:58:05 +02001459 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1460 (void *)msg, length + sizeof(struct tx_desc),
1461 &actual_len, USB_BULK_SEND_TIMEOUT);
Ted Chen9b6dbd42016-01-20 14:24:52 +08001462 debug("Tx: len = %zu, actual = %u, err = %d\n",
1463 length + sizeof(struct tx_desc), actual_len, err);
1464
1465 return err;
1466}
1467
Stefan Roese47c50972016-06-29 07:58:05 +02001468#ifndef CONFIG_DM_ETH
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001469static int r8152_init(struct eth_device *eth, struct bd_info *bd)
Stefan Roese47c50972016-06-29 07:58:05 +02001470{
1471 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1472 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1473
1474 return r8152_init_common(tp);
1475}
1476
1477static int r8152_send(struct eth_device *eth, void *packet, int length)
1478{
1479 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1480
1481 return r8152_send_common(dev, packet, length);
1482}
1483
Ted Chen9b6dbd42016-01-20 14:24:52 +08001484static int r8152_recv(struct eth_device *eth)
1485{
1486 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1487
Stefan Roese01094402016-11-22 16:14:23 +01001488 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
Ted Chen9b6dbd42016-01-20 14:24:52 +08001489 unsigned char *pkt_ptr;
1490 int err;
1491 int actual_len;
1492 u16 packet_len;
1493
1494 u32 bytes_process = 0;
1495 struct rx_desc *rx_desc;
1496
1497 debug("** %s()\n", __func__);
1498
1499 err = usb_bulk_msg(dev->pusb_dev,
1500 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1501 (void *)recv_buf,
1502 RTL8152_AGG_BUF_SZ,
1503 &actual_len,
1504 USB_BULK_RECV_TIMEOUT);
1505 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1506 actual_len, err);
1507 if (err != 0) {
1508 debug("Rx: failed to receive\n");
1509 return -1;
1510 }
1511 if (actual_len > RTL8152_AGG_BUF_SZ) {
1512 debug("Rx: received too many bytes %d\n", actual_len);
1513 return -1;
1514 }
1515
1516 while (bytes_process < actual_len) {
1517 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1518 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1519
1520 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1521 packet_len -= CRC_SIZE;
1522
1523 net_process_received_packet(pkt_ptr, packet_len);
1524
1525 bytes_process +=
1526 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1527
1528 if (bytes_process % 8)
1529 bytes_process = bytes_process + 8 - (bytes_process % 8);
1530 }
1531
1532 return 0;
1533}
1534
1535static void r8152_halt(struct eth_device *eth)
1536{
1537 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1538 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1539
1540 debug("** %s()\n", __func__);
1541
1542 tp->rtl_ops.disable(tp);
1543}
1544
1545static int r8152_write_hwaddr(struct eth_device *eth)
1546{
1547 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1548 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1549
1550 unsigned char enetaddr[8] = {0};
1551
1552 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1553
1554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1555 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1556 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1557
1558 debug("MAC %pM\n", eth->enetaddr);
1559 return 0;
1560}
1561
1562void r8152_eth_before_probe(void)
1563{
1564 curr_eth_dev = 0;
1565}
1566
1567/* Probe to see if a new device is actually an realtek device */
1568int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1569 struct ueth_data *ss)
1570{
1571 struct usb_interface *iface;
1572 struct usb_interface_descriptor *iface_desc;
1573 int ep_in_found = 0, ep_out_found = 0;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001574 struct r8152 *tp;
Hayes Wangf65b6432020-05-22 16:54:10 +08001575 int i;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001576
1577 /* let's examine the device now */
1578 iface = &dev->config.if_desc[ifnum];
1579 iface_desc = &dev->config.if_desc[ifnum].desc;
1580
1581 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1582 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1583 dev->descriptor.idProduct == r8152_dongles[i].product)
1584 /* Found a supported dongle */
1585 break;
1586 }
1587
1588 if (i == ARRAY_SIZE(r8152_dongles))
1589 return 0;
1590
1591 memset(ss, 0, sizeof(struct ueth_data));
1592
1593 /* At this point, we know we've got a live one */
1594 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1595 dev->descriptor.idVendor, dev->descriptor.idProduct);
1596
1597 /* Initialize the ueth_data structure with some useful info */
1598 ss->ifnum = ifnum;
1599 ss->pusb_dev = dev;
1600 ss->subclass = iface_desc->bInterfaceSubClass;
1601 ss->protocol = iface_desc->bInterfaceProtocol;
1602
1603 /* alloc driver private */
1604 ss->dev_priv = calloc(1, sizeof(struct r8152));
1605
1606 if (!ss->dev_priv)
1607 return 0;
1608
1609 /*
1610 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1611 * int. We will ignore any others.
1612 */
1613 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1614 /* is it an BULK endpoint? */
1615 if ((iface->ep_desc[i].bmAttributes &
1616 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1617 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
Hayes Wangf65b6432020-05-22 16:54:10 +08001618
1619 if (ep_addr & USB_DIR_IN) {
1620 if (!ep_in_found) {
1621 ss->ep_in = ep_addr &
1622 USB_ENDPOINT_NUMBER_MASK;
1623 ep_in_found = 1;
1624 }
Ted Chen9b6dbd42016-01-20 14:24:52 +08001625 } else {
1626 if (!ep_out_found) {
1627 ss->ep_out = ep_addr &
1628 USB_ENDPOINT_NUMBER_MASK;
1629 ep_out_found = 1;
1630 }
1631 }
1632 }
1633
1634 /* is it an interrupt endpoint? */
1635 if ((iface->ep_desc[i].bmAttributes &
1636 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1637 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1638 USB_ENDPOINT_NUMBER_MASK;
1639 ss->irqinterval = iface->ep_desc[i].bInterval;
1640 }
1641 }
1642
1643 debug("Endpoints In %d Out %d Int %d\n",
1644 ss->ep_in, ss->ep_out, ss->ep_int);
1645
1646 /* Do some basic sanity checks, and bail if we find a problem */
1647 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1648 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1649 debug("Problems with device\n");
1650 return 0;
1651 }
1652
1653 dev->privptr = (void *)ss;
1654
1655 tp = ss->dev_priv;
1656 tp->udev = dev;
1657 tp->intf = iface;
1658
1659 r8152b_get_version(tp);
1660
1661 if (rtl_ops_init(tp))
1662 return 0;
1663
1664 tp->rtl_ops.init(tp);
1665 tp->rtl_ops.up(tp);
1666
1667 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1668 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1669 DUPLEX_FULL);
1670
1671 return 1;
1672}
1673
1674int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1675 struct eth_device *eth)
1676{
1677 if (!eth) {
1678 debug("%s: missing parameter.\n", __func__);
1679 return 0;
1680 }
1681
1682 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1683 eth->init = r8152_init;
1684 eth->send = r8152_send;
1685 eth->recv = r8152_recv;
1686 eth->halt = r8152_halt;
1687 eth->write_hwaddr = r8152_write_hwaddr;
1688 eth->priv = ss;
1689
1690 /* Get the MAC address */
1691 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1692 return 0;
1693
1694 debug("MAC %pM\n", eth->enetaddr);
1695 return 1;
1696}
Stefan Roese47c50972016-06-29 07:58:05 +02001697#endif /* !CONFIG_DM_ETH */
1698
1699#ifdef CONFIG_DM_ETH
1700static int r8152_eth_start(struct udevice *dev)
1701{
1702 struct r8152 *tp = dev_get_priv(dev);
1703
1704 debug("** %s (%d)\n", __func__, __LINE__);
1705
1706 return r8152_init_common(tp);
1707}
1708
1709void r8152_eth_stop(struct udevice *dev)
1710{
1711 struct r8152 *tp = dev_get_priv(dev);
1712
1713 debug("** %s (%d)\n", __func__, __LINE__);
1714
1715 tp->rtl_ops.disable(tp);
1716}
1717
1718int r8152_eth_send(struct udevice *dev, void *packet, int length)
1719{
1720 struct r8152 *tp = dev_get_priv(dev);
1721
1722 return r8152_send_common(&tp->ueth, packet, length);
1723}
1724
1725int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1726{
1727 struct r8152 *tp = dev_get_priv(dev);
1728 struct ueth_data *ueth = &tp->ueth;
1729 uint8_t *ptr;
1730 int ret, len;
1731 struct rx_desc *rx_desc;
1732 u16 packet_len;
1733
1734 len = usb_ether_get_rx_bytes(ueth, &ptr);
1735 debug("%s: first try, len=%d\n", __func__, len);
1736 if (!len) {
1737 if (!(flags & ETH_RECV_CHECK_DEVICE))
1738 return -EAGAIN;
1739 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1740 if (ret)
1741 return ret;
1742
1743 len = usb_ether_get_rx_bytes(ueth, &ptr);
1744 debug("%s: second try, len=%d\n", __func__, len);
1745 }
1746
1747 rx_desc = (struct rx_desc *)ptr;
1748 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1749 packet_len -= CRC_SIZE;
1750
1751 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1752 debug("Rx: too large packet: %d\n", packet_len);
1753 goto err;
1754 }
1755
1756 *packetp = ptr + sizeof(struct rx_desc);
1757 return packet_len;
1758
1759err:
1760 usb_ether_advance_rxbuf(ueth, -1);
1761 return -ENOSPC;
1762}
1763
1764static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1765{
1766 struct r8152 *tp = dev_get_priv(dev);
1767
1768 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1769 packet_len = ALIGN(packet_len, 8);
1770 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1771
1772 return 0;
1773}
1774
1775static int r8152_write_hwaddr(struct udevice *dev)
1776{
1777 struct eth_pdata *pdata = dev_get_platdata(dev);
1778 struct r8152 *tp = dev_get_priv(dev);
1779
1780 unsigned char enetaddr[8] = { 0 };
1781
1782 debug("** %s (%d)\n", __func__, __LINE__);
1783 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1784
1785 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1786 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1787 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1788
1789 debug("MAC %pM\n", pdata->enetaddr);
1790 return 0;
1791}
1792
1793int r8152_read_rom_hwaddr(struct udevice *dev)
1794{
1795 struct eth_pdata *pdata = dev_get_platdata(dev);
1796 struct r8152 *tp = dev_get_priv(dev);
1797
1798 debug("** %s (%d)\n", __func__, __LINE__);
1799 r8152_read_mac(tp, pdata->enetaddr);
1800 return 0;
1801}
1802
1803static int r8152_eth_probe(struct udevice *dev)
1804{
1805 struct usb_device *udev = dev_get_parent_priv(dev);
1806 struct eth_pdata *pdata = dev_get_platdata(dev);
1807 struct r8152 *tp = dev_get_priv(dev);
1808 struct ueth_data *ueth = &tp->ueth;
1809 int ret;
1810
1811 tp->udev = udev;
1812 r8152_read_mac(tp, pdata->enetaddr);
1813
1814 r8152b_get_version(tp);
1815
1816 ret = rtl_ops_init(tp);
1817 if (ret)
1818 return ret;
1819
1820 tp->rtl_ops.init(tp);
1821 tp->rtl_ops.up(tp);
1822
1823 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1824 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1825 DUPLEX_FULL);
1826
1827 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1828}
1829
1830static const struct eth_ops r8152_eth_ops = {
1831 .start = r8152_eth_start,
1832 .send = r8152_eth_send,
1833 .recv = r8152_eth_recv,
1834 .free_pkt = r8152_free_pkt,
1835 .stop = r8152_eth_stop,
1836 .write_hwaddr = r8152_write_hwaddr,
1837 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1838};
1839
1840U_BOOT_DRIVER(r8152_eth) = {
1841 .name = "r8152_eth",
1842 .id = UCLASS_ETH,
1843 .probe = r8152_eth_probe,
1844 .ops = &r8152_eth_ops,
1845 .priv_auto_alloc_size = sizeof(struct r8152),
1846 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1847};
1848
1849static const struct usb_device_id r8152_eth_id_table[] = {
1850 /* Realtek */
1851 { USB_DEVICE(0x0bda, 0x8050) },
1852 { USB_DEVICE(0x0bda, 0x8152) },
1853 { USB_DEVICE(0x0bda, 0x8153) },
1854
1855 /* Samsung */
1856 { USB_DEVICE(0x04e8, 0xa101) },
1857
1858 /* Lenovo */
1859 { USB_DEVICE(0x17ef, 0x304f) },
1860 { USB_DEVICE(0x17ef, 0x3052) },
1861 { USB_DEVICE(0x17ef, 0x3054) },
1862 { USB_DEVICE(0x17ef, 0x3057) },
1863 { USB_DEVICE(0x17ef, 0x7205) },
1864 { USB_DEVICE(0x17ef, 0x720a) },
1865 { USB_DEVICE(0x17ef, 0x720b) },
1866 { USB_DEVICE(0x17ef, 0x720c) },
1867
1868 /* TP-LINK */
1869 { USB_DEVICE(0x2357, 0x0601) },
1870
1871 /* Nvidia */
1872 { USB_DEVICE(0x0955, 0x09ff) },
1873
1874 { } /* Terminating entry */
1875};
1876
1877U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
1878#endif /* CONFIG_DM_ETH */
1879