blob: 7e8df8795ef3e74973e30e940d3db19f3035e723 [file] [log] [blame]
Simon Glassc036ebd2021-02-06 14:23:35 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <log.h>
9#include <tpm_api.h>
10#include <tpm-v1.h>
11#include <tpm-v2.h>
12#include <tpm_api.h>
13
Simon Glassc036ebd2021-02-06 14:23:35 -070014u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode)
15{
Simon Glass8f2ecaf2022-07-22 21:32:02 +053016 if (tpm_is_v1(dev)) {
Simon Glassc036ebd2021-02-06 14:23:35 -070017 return tpm1_startup(dev, mode);
Simon Glass8f2ecaf2022-07-22 21:32:02 +053018 } else if (tpm_is_v2(dev)) {
Simon Glass1f1eb342021-02-06 14:23:37 -070019 enum tpm2_startup_types type;
20
21 switch (mode) {
22 case TPM_ST_CLEAR:
23 type = TPM2_SU_CLEAR;
24 break;
25 case TPM_ST_STATE:
26 type = TPM2_SU_STATE;
27 break;
28 default:
29 case TPM_ST_DEACTIVATED:
30 return -EINVAL;
31 }
32 return tpm2_startup(dev, type);
33 } else {
Simon Glassc036ebd2021-02-06 14:23:35 -070034 return -ENOSYS;
Simon Glass1f1eb342021-02-06 14:23:37 -070035 }
Simon Glassc036ebd2021-02-06 14:23:35 -070036}
37
38u32 tpm_resume(struct udevice *dev)
39{
Simon Glass8f2ecaf2022-07-22 21:32:02 +053040 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -070041 return tpm1_startup(dev, TPM_ST_STATE);
Simon Glass8f2ecaf2022-07-22 21:32:02 +053042 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -070043 return tpm2_startup(dev, TPM2_SU_STATE);
Simon Glassc036ebd2021-02-06 14:23:35 -070044 else
45 return -ENOSYS;
46}
47
48u32 tpm_self_test_full(struct udevice *dev)
49{
Simon Glass8f2ecaf2022-07-22 21:32:02 +053050 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -070051 return tpm1_self_test_full(dev);
Simon Glass8f2ecaf2022-07-22 21:32:02 +053052 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -070053 return tpm2_self_test(dev, TPMI_YES);
Simon Glassc036ebd2021-02-06 14:23:35 -070054 else
55 return -ENOSYS;
56}
57
58u32 tpm_continue_self_test(struct udevice *dev)
59{
Simon Glass8f2ecaf2022-07-22 21:32:02 +053060 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -070061 return tpm1_continue_self_test(dev);
Simon Glass8f2ecaf2022-07-22 21:32:02 +053062 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -070063 return tpm2_self_test(dev, TPMI_NO);
Simon Glassc036ebd2021-02-06 14:23:35 -070064 else
65 return -ENOSYS;
66}
67
68u32 tpm_clear_and_reenable(struct udevice *dev)
69{
70 u32 ret;
71
72 log_info("TPM: Clear and re-enable\n");
73 ret = tpm_force_clear(dev);
74 if (ret != TPM_SUCCESS) {
75 log_err("Can't initiate a force clear\n");
76 return ret;
77 }
78
Simon Glass8f2ecaf2022-07-22 21:32:02 +053079 if (tpm_is_v1(dev)) {
Simon Glassc036ebd2021-02-06 14:23:35 -070080 ret = tpm1_physical_enable(dev);
81 if (ret != TPM_SUCCESS) {
82 log_err("TPM: Can't set enabled state\n");
83 return ret;
84 }
85
86 ret = tpm1_physical_set_deactivated(dev, 0);
87 if (ret != TPM_SUCCESS) {
88 log_err("TPM: Can't set deactivated state\n");
89 return ret;
90 }
Simon Glassc036ebd2021-02-06 14:23:35 -070091 }
92
93 return TPM_SUCCESS;
94}
95
96u32 tpm_nv_enable_locking(struct udevice *dev)
97{
Simon Glass8f2ecaf2022-07-22 21:32:02 +053098 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -070099 return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530100 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700101 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700102 else
103 return -ENOSYS;
104}
105
106u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count)
107{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530108 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700109 return tpm1_nv_read_value(dev, index, data, count);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530110 else if (tpm_is_v2(dev))
Simon Glass3d930ed2021-02-06 14:23:40 -0700111 return tpm2_nv_read_value(dev, index, data, count);
Simon Glassc036ebd2021-02-06 14:23:35 -0700112 else
113 return -ENOSYS;
114}
115
116u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data,
117 u32 count)
118{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530119 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700120 return tpm1_nv_write_value(dev, index, data, count);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530121 else if (tpm_is_v2(dev))
Simon Glass3d930ed2021-02-06 14:23:40 -0700122 return tpm2_nv_write_value(dev, index, data, count);
Simon Glassc036ebd2021-02-06 14:23:35 -0700123 else
124 return -ENOSYS;
125}
126
127u32 tpm_set_global_lock(struct udevice *dev)
128{
129 return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0);
130}
131
132u32 tpm_write_lock(struct udevice *dev, u32 index)
133{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530134 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700135 return -ENOSYS;
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530136 else if (tpm_is_v2(dev))
Simon Glasse9d3d592021-02-06 14:23:41 -0700137 return tpm2_write_lock(dev, index);
Simon Glassc036ebd2021-02-06 14:23:35 -0700138 else
139 return -ENOSYS;
140}
141
142u32 tpm_pcr_extend(struct udevice *dev, u32 index, const void *in_digest,
Simon Glass4927f472022-08-30 21:05:32 -0600143 uint size, void *out_digest, const char *name)
Simon Glassc036ebd2021-02-06 14:23:35 -0700144{
Simon Glass4927f472022-08-30 21:05:32 -0600145 if (tpm_is_v1(dev)) {
Simon Glassc036ebd2021-02-06 14:23:35 -0700146 return tpm1_extend(dev, index, in_digest, out_digest);
Simon Glass4927f472022-08-30 21:05:32 -0600147 } else if (tpm_is_v2(dev)) {
Simon Glass1f1eb342021-02-06 14:23:37 -0700148 return tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, in_digest,
149 TPM2_DIGEST_LEN);
Simon Glass4927f472022-08-30 21:05:32 -0600150 /* @name is ignored as we do not support the TPM log here */
151 } else {
Simon Glassc036ebd2021-02-06 14:23:35 -0700152 return -ENOSYS;
Simon Glass4927f472022-08-30 21:05:32 -0600153 }
Simon Glassc036ebd2021-02-06 14:23:35 -0700154}
155
156u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count)
157{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530158 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700159 return tpm1_pcr_read(dev, index, data, count);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530160 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700161 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700162 else
163 return -ENOSYS;
164}
165
166u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence)
167{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530168 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700169 return tpm1_tsc_physical_presence(dev, presence);
Simon Glass1f1eb342021-02-06 14:23:37 -0700170
171 /*
172 * Nothing to do on TPM2 for this; use platform hierarchy availability
173 * instead.
174 */
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530175 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700176 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700177 else
178 return -ENOSYS;
179}
180
181u32 tpm_finalise_physical_presence(struct udevice *dev)
182{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530183 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700184 return tpm1_finalise_physical_presence(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700185
186 /* Nothing needs to be done with tpm2 */
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530187 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700188 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700189 else
190 return -ENOSYS;
191}
192
193u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count)
194{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530195 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700196 return tpm1_read_pubek(dev, data, count);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530197 else if (tpm_is_v2(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700198 return -ENOSYS; /* not implemented yet */
Simon Glass1f1eb342021-02-06 14:23:37 -0700199 else
200 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700201}
202
203u32 tpm_force_clear(struct udevice *dev)
204{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530205 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700206 return tpm1_force_clear(dev);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530207 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700208 return tpm2_clear(dev, TPM2_RH_PLATFORM, NULL, 0);
Simon Glassc036ebd2021-02-06 14:23:35 -0700209 else
210 return -ENOSYS;
211}
212
213u32 tpm_physical_enable(struct udevice *dev)
214{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530215 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700216 return tpm1_physical_enable(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700217
218 /* Nothing needs to be done with tpm2 */
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530219 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700220 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700221 else
222 return -ENOSYS;
223}
224
225u32 tpm_physical_disable(struct udevice *dev)
226{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530227 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700228 return tpm1_physical_disable(dev);
Simon Glass1f1eb342021-02-06 14:23:37 -0700229
230 /* Nothing needs to be done with tpm2 */
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530231 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700232 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700233 else
234 return -ENOSYS;
235}
236
237u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state)
238{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530239 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700240 return tpm1_physical_set_deactivated(dev, state);
Simon Glass1f1eb342021-02-06 14:23:37 -0700241 /* Nothing needs to be done with tpm2 */
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530242 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700243 return 0;
Simon Glassc036ebd2021-02-06 14:23:35 -0700244 else
245 return -ENOSYS;
246}
247
248u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap,
249 void *cap, size_t count)
250{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530251 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700252 return tpm1_get_capability(dev, cap_area, sub_cap, cap, count);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530253 else if (tpm_is_v2(dev))
Simon Glass1f1eb342021-02-06 14:23:37 -0700254 return tpm2_get_capability(dev, cap_area, sub_cap, cap, count);
Simon Glassc036ebd2021-02-06 14:23:35 -0700255 else
256 return -ENOSYS;
257}
258
259u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm)
260{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530261 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700262 return tpm1_get_permissions(dev, index, perm);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530263 else if (tpm_is_v2(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700264 return -ENOSYS; /* not implemented yet */
Simon Glass1f1eb342021-02-06 14:23:37 -0700265 else
266 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700267}
268
269u32 tpm_get_random(struct udevice *dev, void *data, u32 count)
270{
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530271 if (tpm_is_v1(dev))
Simon Glassc036ebd2021-02-06 14:23:35 -0700272 return tpm1_get_random(dev, data, count);
Simon Glass8f2ecaf2022-07-22 21:32:02 +0530273 else if (tpm_is_v2(dev))
Sughosh Ganu9737fab2022-07-22 21:32:04 +0530274 return tpm2_get_random(dev, data, count);
275
276 return -ENOSYS;
Simon Glassc036ebd2021-02-06 14:23:35 -0700277}