Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <log.h> |
| 9 | #include <tpm_api.h> |
| 10 | #include <tpm-v1.h> |
| 11 | #include <tpm-v2.h> |
| 12 | #include <tpm_api.h> |
| 13 | |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 14 | u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode) |
| 15 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 16 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 17 | return tpm1_startup(dev, mode); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 18 | } else if (tpm_is_v2(dev)) { |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 19 | enum tpm2_startup_types type; |
| 20 | |
| 21 | switch (mode) { |
| 22 | case TPM_ST_CLEAR: |
| 23 | type = TPM2_SU_CLEAR; |
| 24 | break; |
| 25 | case TPM_ST_STATE: |
| 26 | type = TPM2_SU_STATE; |
| 27 | break; |
| 28 | default: |
| 29 | case TPM_ST_DEACTIVATED: |
| 30 | return -EINVAL; |
| 31 | } |
| 32 | return tpm2_startup(dev, type); |
| 33 | } else { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 34 | return -ENOSYS; |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 35 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | u32 tpm_resume(struct udevice *dev) |
| 39 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 40 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 41 | return tpm1_startup(dev, TPM_ST_STATE); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 42 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 43 | return tpm2_startup(dev, TPM2_SU_STATE); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 44 | else |
| 45 | return -ENOSYS; |
| 46 | } |
| 47 | |
| 48 | u32 tpm_self_test_full(struct udevice *dev) |
| 49 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 50 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 51 | return tpm1_self_test_full(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 52 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 53 | return tpm2_self_test(dev, TPMI_YES); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 54 | else |
| 55 | return -ENOSYS; |
| 56 | } |
| 57 | |
| 58 | u32 tpm_continue_self_test(struct udevice *dev) |
| 59 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 60 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 61 | return tpm1_continue_self_test(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 62 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 63 | return tpm2_self_test(dev, TPMI_NO); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 64 | else |
| 65 | return -ENOSYS; |
| 66 | } |
| 67 | |
| 68 | u32 tpm_clear_and_reenable(struct udevice *dev) |
| 69 | { |
| 70 | u32 ret; |
| 71 | |
| 72 | log_info("TPM: Clear and re-enable\n"); |
| 73 | ret = tpm_force_clear(dev); |
| 74 | if (ret != TPM_SUCCESS) { |
| 75 | log_err("Can't initiate a force clear\n"); |
| 76 | return ret; |
| 77 | } |
| 78 | |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 79 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 80 | ret = tpm1_physical_enable(dev); |
| 81 | if (ret != TPM_SUCCESS) { |
| 82 | log_err("TPM: Can't set enabled state\n"); |
| 83 | return ret; |
| 84 | } |
| 85 | |
| 86 | ret = tpm1_physical_set_deactivated(dev, 0); |
| 87 | if (ret != TPM_SUCCESS) { |
| 88 | log_err("TPM: Can't set deactivated state\n"); |
| 89 | return ret; |
| 90 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | return TPM_SUCCESS; |
| 94 | } |
| 95 | |
| 96 | u32 tpm_nv_enable_locking(struct udevice *dev) |
| 97 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 98 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 99 | return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 100 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 101 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 102 | else |
| 103 | return -ENOSYS; |
| 104 | } |
| 105 | |
| 106 | u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count) |
| 107 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 108 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 109 | return tpm1_nv_read_value(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 110 | else if (tpm_is_v2(dev)) |
Simon Glass | 3d930ed | 2021-02-06 14:23:40 -0700 | [diff] [blame] | 111 | return tpm2_nv_read_value(dev, index, data, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 112 | else |
| 113 | return -ENOSYS; |
| 114 | } |
| 115 | |
| 116 | u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data, |
| 117 | u32 count) |
| 118 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 119 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 120 | return tpm1_nv_write_value(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 121 | else if (tpm_is_v2(dev)) |
Simon Glass | 3d930ed | 2021-02-06 14:23:40 -0700 | [diff] [blame] | 122 | return tpm2_nv_write_value(dev, index, data, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 123 | else |
| 124 | return -ENOSYS; |
| 125 | } |
| 126 | |
| 127 | u32 tpm_set_global_lock(struct udevice *dev) |
| 128 | { |
| 129 | return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0); |
| 130 | } |
| 131 | |
| 132 | u32 tpm_write_lock(struct udevice *dev, u32 index) |
| 133 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 134 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 135 | return -ENOSYS; |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 136 | else if (tpm_is_v2(dev)) |
Simon Glass | e9d3d59 | 2021-02-06 14:23:41 -0700 | [diff] [blame] | 137 | return tpm2_write_lock(dev, index); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 138 | else |
| 139 | return -ENOSYS; |
| 140 | } |
| 141 | |
| 142 | u32 tpm_pcr_extend(struct udevice *dev, u32 index, const void *in_digest, |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 143 | uint size, void *out_digest, const char *name) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 144 | { |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 145 | if (tpm_is_v1(dev)) { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 146 | return tpm1_extend(dev, index, in_digest, out_digest); |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 147 | } else if (tpm_is_v2(dev)) { |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 148 | return tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, in_digest, |
| 149 | TPM2_DIGEST_LEN); |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 150 | /* @name is ignored as we do not support the TPM log here */ |
| 151 | } else { |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 152 | return -ENOSYS; |
Simon Glass | 4927f47 | 2022-08-30 21:05:32 -0600 | [diff] [blame] | 153 | } |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count) |
| 157 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 158 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 159 | return tpm1_pcr_read(dev, index, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 160 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 161 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 162 | else |
| 163 | return -ENOSYS; |
| 164 | } |
| 165 | |
| 166 | u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence) |
| 167 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 168 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 169 | return tpm1_tsc_physical_presence(dev, presence); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 170 | |
| 171 | /* |
| 172 | * Nothing to do on TPM2 for this; use platform hierarchy availability |
| 173 | * instead. |
| 174 | */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 175 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 176 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 177 | else |
| 178 | return -ENOSYS; |
| 179 | } |
| 180 | |
| 181 | u32 tpm_finalise_physical_presence(struct udevice *dev) |
| 182 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 183 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 184 | return tpm1_finalise_physical_presence(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 185 | |
| 186 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 187 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 188 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 189 | else |
| 190 | return -ENOSYS; |
| 191 | } |
| 192 | |
| 193 | u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count) |
| 194 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 195 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 196 | return tpm1_read_pubek(dev, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 197 | else if (tpm_is_v2(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 198 | return -ENOSYS; /* not implemented yet */ |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 199 | else |
| 200 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | u32 tpm_force_clear(struct udevice *dev) |
| 204 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 205 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 206 | return tpm1_force_clear(dev); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 207 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 208 | return tpm2_clear(dev, TPM2_RH_PLATFORM, NULL, 0); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 209 | else |
| 210 | return -ENOSYS; |
| 211 | } |
| 212 | |
| 213 | u32 tpm_physical_enable(struct udevice *dev) |
| 214 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 215 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 216 | return tpm1_physical_enable(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 217 | |
| 218 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 219 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 220 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 221 | else |
| 222 | return -ENOSYS; |
| 223 | } |
| 224 | |
| 225 | u32 tpm_physical_disable(struct udevice *dev) |
| 226 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 227 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 228 | return tpm1_physical_disable(dev); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 229 | |
| 230 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 231 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 232 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 233 | else |
| 234 | return -ENOSYS; |
| 235 | } |
| 236 | |
| 237 | u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state) |
| 238 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 239 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 240 | return tpm1_physical_set_deactivated(dev, state); |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 241 | /* Nothing needs to be done with tpm2 */ |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 242 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 243 | return 0; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 244 | else |
| 245 | return -ENOSYS; |
| 246 | } |
| 247 | |
| 248 | u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap, |
| 249 | void *cap, size_t count) |
| 250 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 251 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 252 | return tpm1_get_capability(dev, cap_area, sub_cap, cap, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 253 | else if (tpm_is_v2(dev)) |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 254 | return tpm2_get_capability(dev, cap_area, sub_cap, cap, count); |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 255 | else |
| 256 | return -ENOSYS; |
| 257 | } |
| 258 | |
| 259 | u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm) |
| 260 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 261 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 262 | return tpm1_get_permissions(dev, index, perm); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 263 | else if (tpm_is_v2(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 264 | return -ENOSYS; /* not implemented yet */ |
Simon Glass | 1f1eb34 | 2021-02-06 14:23:37 -0700 | [diff] [blame] | 265 | else |
| 266 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | u32 tpm_get_random(struct udevice *dev, void *data, u32 count) |
| 270 | { |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 271 | if (tpm_is_v1(dev)) |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 272 | return tpm1_get_random(dev, data, count); |
Simon Glass | 8f2ecaf | 2022-07-22 21:32:02 +0530 | [diff] [blame] | 273 | else if (tpm_is_v2(dev)) |
Sughosh Ganu | 9737fab | 2022-07-22 21:32:04 +0530 | [diff] [blame] | 274 | return tpm2_get_random(dev, data, count); |
| 275 | |
| 276 | return -ENOSYS; |
Simon Glass | c036ebd | 2021-02-06 14:23:35 -0700 | [diff] [blame] | 277 | } |