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git01.mediatek.com / filogic / uboot / 9ac1d83d5b87e667a2c51980641a0c5080ceb338 / . / drivers / pinctrl / rockchip / pinctrl_rk3368.c
blob: c96459ff573a485729109e249d6589a09b264ef3 [file] [log] [blame]
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]1/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <dm.h>
8#include <errno.h>
9#include <syscon.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/hardware.h>
13#include <asm/arch/grf_rk3368.h>
14#include <asm/arch/periph.h>
15#include <dm/pinctrl.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct rk3368_pinctrl_priv {
20 struct rk3368_grf *grf;
21 struct rk3368_pmu_grf *pmugrf;
22};
23
24static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
25 int uart_id)
26{
27 struct rk3368_grf *grf = priv->grf;
28 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
29
30 switch (uart_id) {
31 case PERIPH_ID_UART2:
32 rk_clrsetreg(&grf->gpio2a_iomux,
33 GPIO2A6_MASK | GPIO2A5_MASK,
Philipp Tomsich9ac1d832017-07-25 17:01:06 +0200[diff] [blame^]34 GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]35 break;
36 case PERIPH_ID_UART0:
37 break;
38 case PERIPH_ID_UART1:
39 break;
40 case PERIPH_ID_UART3:
41 break;
42 case PERIPH_ID_UART4:
43 rk_clrsetreg(&pmugrf->gpio0d_iomux,
44 GPIO0D0_MASK | GPIO0D1_MASK |
45 GPIO0D2_MASK | GPIO0D3_MASK,
Philipp Tomsich9ac1d832017-07-25 17:01:06 +0200[diff] [blame^]46 GPIO0D0_GPIO | GPIO0D1_GPIO |
47 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]48 break;
49 default:
50 debug("uart id = %d iomux error!\n", uart_id);
51 break;
52 }
53}
54
55static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
56{
57 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
58
59 debug("%s: func=%d, flags=%x\n", __func__, func, flags);
60 switch (func) {
61 case PERIPH_ID_UART0:
62 case PERIPH_ID_UART1:
63 case PERIPH_ID_UART2:
64 case PERIPH_ID_UART3:
65 case PERIPH_ID_UART4:
66 pinctrl_rk3368_uart_config(priv, func);
67 break;
68 default:
69 return -EINVAL;
70 }
71
72 return 0;
73}
74
75static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
76 struct udevice *periph)
77{
78 u32 cell[3];
79 int ret;
80
81 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
82 "interrupts", cell, ARRAY_SIZE(cell));
83 if (ret < 0)
84 return -EINVAL;
85
86 switch (cell[1]) {
87 case 59:
88 return PERIPH_ID_UART4;
89 case 58:
90 return PERIPH_ID_UART3;
91 case 57:
92 return PERIPH_ID_UART2;
93 case 56:
94 return PERIPH_ID_UART1;
95 case 55:
96 return PERIPH_ID_UART0;
97 }
98
99 return -ENOENT;
100}
101
102static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
103 struct udevice *periph)
104{
105 int func;
106
107 func = rk3368_pinctrl_get_periph_id(dev, periph);
108 if (func < 0)
109 return func;
110
111 return rk3368_pinctrl_request(dev, func, 0);
112}
113
114static struct pinctrl_ops rk3368_pinctrl_ops = {
115 .set_state_simple = rk3368_pinctrl_set_state_simple,
116 .request = rk3368_pinctrl_request,
117 .get_periph_id = rk3368_pinctrl_get_periph_id,
118};
119
120static int rk3368_pinctrl_probe(struct udevice *dev)
121{
122 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
123 int ret = 0;
124
125 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
126 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
127
128 debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
129
130 return ret;
131}
132
133static const struct udevice_id rk3368_pinctrl_ids[] = {
134 { .compatible = "rockchip,rk3368-pinctrl" },
135 { }
136};
137
138U_BOOT_DRIVER(pinctrl_rk3368) = {
139 .name = "rockchip_rk3368_pinctrl",
140 .id = UCLASS_PINCTRL,
141 .of_match = rk3368_pinctrl_ids,
142 .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
143 .ops = &rk3368_pinctrl_ops,
144 .bind = dm_scan_fdt_dev,
145 .probe = rk3368_pinctrl_probe,
146};