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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese312dc932016-08-15 13:50:49 +02002/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
Stefan Roese312dc932016-08-15 13:50:49 +02005 */
6
Bin Meng497c5162017-05-31 01:04:14 -07007#include <asm/arch-baytrail/fsp/fsp_configs.h>
Stefan Roese312dc932016-08-15 13:50:49 +02008#include <dt-bindings/gpio/x86-gpio.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11#include "skeleton.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -070012#include "reset.dtsi"
Stefan Roese312dc932016-08-15 13:50:49 +020013#include "rtc.dtsi"
14#include "tsc_timer.dtsi"
15
Simon Glassbee77f62020-11-05 06:32:17 -070016#include "smbios.dtsi"
17
Stefan Roese312dc932016-08-15 13:50:49 +020018/ {
19 config {
20 silent_console = <0>;
21 };
22
23 pch_pinctrl {
24 compatible = "intel,x86-pinctrl";
25 reg = <0 0>;
26
27 /* Add UART1 PAD configuration (SIO HS-UART) */
28 uart1_txd@0 {
29 pad-offset = <0x10>;
30 mode-func = <1>;
31 };
32
33 uart1_rxd@0 {
34 pad-offset = <0x20>;
35 mode-func = <1>;
36 };
37
38 /*
39 * As of today, the latest version FSP (gold4) for BayTrail
40 * misses the PAD configuration of the SD controller's Card
41 * Detect signal. The default PAD value for the CD pin sets
42 * the pin to work in GPIO mode, which causes card detect
43 * status cannot be reflected by the Present State register
44 * in the SD controller (bit 16 & bit 18 are always zero).
45 *
46 * Configure this pin to function 1 (SD controller).
47 */
48 sdmmc3_cd@0 {
49 pad-offset = <0x3a0>;
50 mode-func = <1>;
51 };
Stefan Roese0700bba2017-07-18 14:10:49 +020052
53 xhci_hub_reset: usb_ulpi_stp@0 {
54 gpio-offset = <0xa0 10>;
55 pad-offset = <0x23b0>;
56 mode-func = <0>;
57 mode-gpio;
58 output-value = <1>;
59 direction = <PIN_OUTPUT>;
60 };
Stefan Roese312dc932016-08-15 13:50:49 +020061 };
62
63 chosen {
64 stdout-path = "/serial";
65 };
66
67 cpus {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 cpu@0 {
72 device_type = "cpu";
73 compatible = "intel,baytrail-cpu";
74 reg = <0>;
75 intel,apic-id = <0>;
76 };
77
78 cpu@1 {
79 device_type = "cpu";
80 compatible = "intel,baytrail-cpu";
81 reg = <1>;
82 intel,apic-id = <2>;
83 };
84
85 cpu@2 {
86 device_type = "cpu";
87 compatible = "intel,baytrail-cpu";
88 reg = <2>;
89 intel,apic-id = <4>;
90 };
91
92 cpu@3 {
93 device_type = "cpu";
94 compatible = "intel,baytrail-cpu";
95 reg = <3>;
96 intel,apic-id = <6>;
97 };
98 };
99
100 pci {
101 compatible = "intel,pci-baytrail", "pci-x86";
102 #address-cells = <3>;
103 #size-cells = <2>;
104 u-boot,dm-pre-reloc;
105 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
106 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
107 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
108
109 pciuart0: uart@1e,3 {
110 compatible = "pci8086,0f0a.00",
111 "pci8086,0f0a",
112 "pciclass,070002",
113 "pciclass,0700",
114 "ns16550";
115 u-boot,dm-pre-reloc;
116 reg = <0x0200f310 0x0 0x0 0x0 0x0>;
117 reg-shift = <2>;
118 clock-frequency = <58982400>;
119 current-speed = <115200>;
120 };
121
122 pch@1f,0 {
123 reg = <0x0000f800 0 0 0 0>;
124 compatible = "pci8086,0f1c", "intel,pch9";
125 #address-cells = <1>;
126 #size-cells = <1>;
127
128 irq-router {
129 compatible = "intel,irq-router";
130 intel,pirq-config = "ibase";
131 intel,ibase-offset = <0x50>;
132 intel,actl-addr = <0>;
133 intel,pirq-link = <8 8>;
134 intel,pirq-mask = <0xdee0>;
135 intel,pirq-routing = <
136 /* BayTrail PCI devices */
137 PCI_BDF(0, 2, 0) INTA PIRQA
138 PCI_BDF(0, 3, 0) INTA PIRQA
139 PCI_BDF(0, 16, 0) INTA PIRQA
140 PCI_BDF(0, 17, 0) INTA PIRQA
141 PCI_BDF(0, 18, 0) INTA PIRQA
142 PCI_BDF(0, 19, 0) INTA PIRQA
143 PCI_BDF(0, 20, 0) INTA PIRQA
144 PCI_BDF(0, 21, 0) INTA PIRQA
145 PCI_BDF(0, 22, 0) INTA PIRQA
146 PCI_BDF(0, 23, 0) INTA PIRQA
147 PCI_BDF(0, 24, 0) INTA PIRQA
148 PCI_BDF(0, 24, 1) INTC PIRQC
149 PCI_BDF(0, 24, 2) INTD PIRQD
150 PCI_BDF(0, 24, 3) INTB PIRQB
151 PCI_BDF(0, 24, 4) INTA PIRQA
152 PCI_BDF(0, 24, 5) INTC PIRQC
153 PCI_BDF(0, 24, 6) INTD PIRQD
154 PCI_BDF(0, 24, 7) INTB PIRQB
155 PCI_BDF(0, 26, 0) INTA PIRQA
156 PCI_BDF(0, 27, 0) INTA PIRQA
157 PCI_BDF(0, 28, 0) INTA PIRQA
158 PCI_BDF(0, 28, 1) INTB PIRQB
159 PCI_BDF(0, 28, 2) INTC PIRQC
160 PCI_BDF(0, 28, 3) INTD PIRQD
161 PCI_BDF(0, 29, 0) INTA PIRQA
162 PCI_BDF(0, 30, 0) INTA PIRQA
163 PCI_BDF(0, 30, 1) INTD PIRQD
164 PCI_BDF(0, 30, 2) INTB PIRQB
165 PCI_BDF(0, 30, 3) INTC PIRQC
166 PCI_BDF(0, 30, 4) INTD PIRQD
167 PCI_BDF(0, 30, 5) INTB PIRQB
168 PCI_BDF(0, 31, 3) INTB PIRQB
169
170 /*
171 * PCIe root ports downstream
172 * interrupts
173 */
174 PCI_BDF(1, 0, 0) INTA PIRQA
175 PCI_BDF(1, 0, 0) INTB PIRQB
176 PCI_BDF(1, 0, 0) INTC PIRQC
177 PCI_BDF(1, 0, 0) INTD PIRQD
178 PCI_BDF(2, 0, 0) INTA PIRQB
179 PCI_BDF(2, 0, 0) INTB PIRQC
180 PCI_BDF(2, 0, 0) INTC PIRQD
181 PCI_BDF(2, 0, 0) INTD PIRQA
182 PCI_BDF(3, 0, 0) INTA PIRQC
183 PCI_BDF(3, 0, 0) INTB PIRQD
184 PCI_BDF(3, 0, 0) INTC PIRQA
185 PCI_BDF(3, 0, 0) INTD PIRQB
186 PCI_BDF(4, 0, 0) INTA PIRQD
187 PCI_BDF(4, 0, 0) INTB PIRQA
188 PCI_BDF(4, 0, 0) INTC PIRQB
189 PCI_BDF(4, 0, 0) INTD PIRQC
190 >;
191 };
192
193 spi: spi {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "intel,ich9-spi";
197 spi-flash@0 {
198 #address-cells = <1>;
199 #size-cells = <1>;
200 reg = <0>;
Bin Mengac54e252021-07-29 20:18:23 +0800201 m25p,fast-read;
Stefan Roese312dc932016-08-15 13:50:49 +0200202 compatible = "stmicro,n25q064a",
Neil Armstrongf6625b42019-02-10 10:16:21 +0000203 "jedec,spi-nor";
Stefan Roese312dc932016-08-15 13:50:49 +0200204 memory-map = <0xff800000 0x00800000>;
205 rw-mrc-cache {
206 label = "rw-mrc-cache";
Simon Glass9a6efd52023-03-14 17:59:54 -0600207 reg = <0x005f0000 0x00010000>;
Stefan Roese312dc932016-08-15 13:50:49 +0200208 };
209 };
210 };
211
212 gpioa {
213 compatible = "intel,ich6-gpio";
214 u-boot,dm-pre-reloc;
215 reg = <0 0x20>;
216 bank-name = "A";
Bin Meng59be2c02017-05-07 19:52:29 -0700217 use-lvl-write-cache;
Stefan Roese312dc932016-08-15 13:50:49 +0200218 };
219
220 gpiob {
221 compatible = "intel,ich6-gpio";
222 u-boot,dm-pre-reloc;
223 reg = <0x20 0x20>;
224 bank-name = "B";
Bin Meng59be2c02017-05-07 19:52:29 -0700225 use-lvl-write-cache;
Stefan Roese312dc932016-08-15 13:50:49 +0200226 };
227
228 gpioc {
229 compatible = "intel,ich6-gpio";
230 u-boot,dm-pre-reloc;
231 reg = <0x40 0x20>;
232 bank-name = "C";
Bin Meng59be2c02017-05-07 19:52:29 -0700233 use-lvl-write-cache;
Stefan Roese312dc932016-08-15 13:50:49 +0200234 };
235
236 gpiod {
237 compatible = "intel,ich6-gpio";
238 u-boot,dm-pre-reloc;
239 reg = <0x60 0x20>;
240 bank-name = "D";
Bin Meng59be2c02017-05-07 19:52:29 -0700241 use-lvl-write-cache;
Stefan Roese312dc932016-08-15 13:50:49 +0200242 };
243
244 gpioe {
245 compatible = "intel,ich6-gpio";
246 u-boot,dm-pre-reloc;
247 reg = <0x80 0x20>;
248 bank-name = "E";
Bin Meng59be2c02017-05-07 19:52:29 -0700249 use-lvl-write-cache;
Stefan Roese312dc932016-08-15 13:50:49 +0200250 };
251
252 gpiof {
253 compatible = "intel,ich6-gpio";
254 u-boot,dm-pre-reloc;
255 reg = <0xA0 0x20>;
256 bank-name = "F";
Bin Meng59be2c02017-05-07 19:52:29 -0700257 use-lvl-write-cache;
Stefan Roese312dc932016-08-15 13:50:49 +0200258 };
259 };
260 };
261
262 fsp {
263 compatible = "intel,baytrail-fsp";
Bin Meng497c5162017-05-31 01:04:14 -0700264 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
265 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
Stefan Roese312dc932016-08-15 13:50:49 +0200266 fsp,mrc-init-spd-addr1 = <0xa0>;
267 fsp,mrc-init-spd-addr2 = <0xa2>;
Bin Meng497c5162017-05-31 01:04:14 -0700268 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
Stefan Roese312dc932016-08-15 13:50:49 +0200269 fsp,enable-sdio;
270 fsp,enable-sdcard;
271 fsp,enable-hsuart0;
272 fsp,enable-hsuart1;
273 fsp,enable-spi;
274 fsp,enable-sata;
Bin Meng497c5162017-05-31 01:04:14 -0700275 fsp,sata-mode = <SATA_MODE_AHCI>;
Stefan Roese0700bba2017-07-18 14:10:49 +0200276#ifdef CONFIG_USB_XHCI_HCD
277 fsp,enable-xhci;
278#endif
Bin Menge5bf9692017-05-31 01:04:15 -0700279 fsp,lpe-mode = <LPE_MODE_PCI>;
280 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
Stefan Roese312dc932016-08-15 13:50:49 +0200281 fsp,enable-dma0;
282 fsp,enable-dma1;
283 fsp,enable-i2c0;
284 fsp,enable-i2c1;
285 fsp,enable-i2c2;
286 fsp,enable-i2c3;
287 fsp,enable-i2c4;
288 fsp,enable-i2c5;
289 fsp,enable-i2c6;
290 fsp,enable-pwm0;
291 fsp,enable-pwm1;
Bin Meng497c5162017-05-31 01:04:14 -0700292 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
293 fsp,aperture-size = <APERTURE_SIZE_256MB>;
294 fsp,gtt-size = <GTT_SIZE_2MB>;
Bin Menge5bf9692017-05-31 01:04:15 -0700295 fsp,scc-mode = <SCC_MODE_PCI>;
Bin Meng497c5162017-05-31 01:04:14 -0700296 fsp,os-selection = <OS_SELECTION_LINUX>;
Stefan Roese312dc932016-08-15 13:50:49 +0200297 fsp,emmc45-ddr50-enabled;
298 fsp,emmc45-retune-timer-value = <8>;
299 fsp,enable-igd;
300 fsp,enable-memory-down;
301 fsp,memory-down-params {
302 compatible = "intel,baytrail-fsp-mdp";
Bin Meng497c5162017-05-31 01:04:14 -0700303 fsp,dram-speed = <DRAM_SPEED_1333MTS>;
304 fsp,dram-type = <DRAM_TYPE_DDR3L>;
Stefan Roese312dc932016-08-15 13:50:49 +0200305 fsp,dimm-0-enable;
Bin Meng497c5162017-05-31 01:04:14 -0700306 fsp,dimm-width = <DIMM_WIDTH_X16>;
307 fsp,dimm-density = <DIMM_DENSITY_8GBIT>;
308 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
309 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
Stefan Roese312dc932016-08-15 13:50:49 +0200310
311 /* These following values might need a re-visit */
312 fsp,dimm-tcl = <8>;
313 fsp,dimm-trpt-rcd = <8>;
314 fsp,dimm-twr = <8>;
315 fsp,dimm-twtr = <4>;
316 fsp,dimm-trrd = <6>;
317 fsp,dimm-trtp = <4>;
318 fsp,dimm-tfaw = <22>;
319 };
320 };
321
322 microcode {
323 update@0 {
324#include "microcode/m0130673325.dtsi"
325 };
326 update@1 {
327#include "microcode/m0130679907.dtsi"
328 };
329 };
330};