Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
Hongbo Zhang | 4f6e610 | 2016-07-21 18:09:38 +0800 | [diff] [blame] | 10 | #define CONFIG_ARMV7_PSCI_1_0 |
Wang Dongsheng | 13d2bb7 | 2015-06-04 12:01:09 +0800 | [diff] [blame] | 11 | |
Hongbo Zhang | 912b381 | 2016-07-21 18:09:39 +0800 | [diff] [blame] | 12 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
| 13 | |
Gong Qianyu | 52de2e5 | 2015-10-26 19:47:42 +0800 | [diff] [blame] | 14 | #define CONFIG_SYS_FSL_CLK |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 15 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 16 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Tang Yuantian | 8b160bc | 2015-05-14 17:20:28 +0800 | [diff] [blame] | 17 | #define CONFIG_DEEP_SLEEP |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 18 | |
| 19 | /* |
| 20 | * Size of malloc() pool |
| 21 | */ |
| 22 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) |
| 23 | |
| 24 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR |
| 25 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE |
| 26 | |
| 27 | /* |
Ramneek Mehresh | eed80b0 | 2015-05-29 14:47:21 +0530 | [diff] [blame] | 28 | * USB |
| 29 | */ |
| 30 | |
| 31 | /* |
| 32 | * EHCI Support - disbaled by default as |
| 33 | * there is no signal coming out of soc on |
| 34 | * this board for this controller. However, |
| 35 | * the silicon still has this controller, |
| 36 | * and anyone can use this controller by |
| 37 | * taking signals out on their board. |
| 38 | */ |
| 39 | |
| 40 | /*#define CONFIG_HAS_FSL_DR_USB*/ |
| 41 | |
| 42 | #ifdef CONFIG_HAS_FSL_DR_USB |
Ramneek Mehresh | eed80b0 | 2015-05-29 14:47:21 +0530 | [diff] [blame] | 43 | #define CONFIG_USB_EHCI_FSL |
| 44 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 45 | #endif |
| 46 | |
| 47 | /* XHCI Support - enabled by default */ |
| 48 | #define CONFIG_HAS_FSL_XHCI_USB |
| 49 | |
| 50 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
| 51 | #define CONFIG_USB_XHCI_FSL |
Ramneek Mehresh | eed80b0 | 2015-05-29 14:47:21 +0530 | [diff] [blame] | 52 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
Ramneek Mehresh | eed80b0 | 2015-05-29 14:47:21 +0530 | [diff] [blame] | 53 | #endif |
| 54 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 55 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 56 | #define CONFIG_DDR_CLK_FREQ 100000000 |
| 57 | |
York Sun | 1006cad | 2015-04-29 10:35:35 -0700 | [diff] [blame] | 58 | #define DDR_SDRAM_CFG 0x470c0008 |
| 59 | #define DDR_CS0_BNDS 0x008000bf |
| 60 | #define DDR_CS0_CONFIG 0x80014302 |
| 61 | #define DDR_TIMING_CFG_0 0x50550004 |
| 62 | #define DDR_TIMING_CFG_1 0xbcb38c56 |
| 63 | #define DDR_TIMING_CFG_2 0x0040d120 |
| 64 | #define DDR_TIMING_CFG_3 0x010e1000 |
| 65 | #define DDR_TIMING_CFG_4 0x00000001 |
| 66 | #define DDR_TIMING_CFG_5 0x03401400 |
| 67 | #define DDR_SDRAM_CFG_2 0x00401010 |
| 68 | #define DDR_SDRAM_MODE 0x00061c60 |
| 69 | #define DDR_SDRAM_MODE_2 0x00180000 |
| 70 | #define DDR_SDRAM_INTERVAL 0x18600618 |
| 71 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 |
| 72 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 |
| 73 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 |
| 74 | #define DDR_DDR_CDR1 0x80040000 |
| 75 | #define DDR_DDR_CDR2 0x00000001 |
| 76 | #define DDR_SDRAM_CLK_CNTL 0x02000000 |
| 77 | #define DDR_DDR_ZQ_CNTL 0x89080600 |
| 78 | #define DDR_CS0_CONFIG_2 0 |
| 79 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 |
Tang Yuantian | 8b160bc | 2015-05-14 17:20:28 +0800 | [diff] [blame] | 80 | #define SDRAM_CFG2_D_INIT 0x00000010 |
| 81 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 |
| 82 | #define SDRAM_CFG2_FRC_SR 0x80000000 |
| 83 | #define SDRAM_CFG_BI 0x00000001 |
York Sun | 1006cad | 2015-04-29 10:35:35 -0700 | [diff] [blame] | 84 | |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 85 | #ifdef CONFIG_RAMBOOT_PBL |
| 86 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg |
| 87 | #endif |
| 88 | |
| 89 | #ifdef CONFIG_SD_BOOT |
Alison Wang | dd45cc5 | 2015-10-15 17:54:40 +0800 | [diff] [blame] | 90 | #ifdef CONFIG_SD_BOOT_QSPI |
| 91 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 92 | board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg |
| 93 | #else |
| 94 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 95 | board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg |
| 96 | #endif |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 97 | #define CONFIG_SPL_FRAMEWORK |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 98 | |
| 99 | #ifdef CONFIG_SECURE_BOOT |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 100 | /* |
| 101 | * HDR would be appended at end of image and copied to DDR along |
| 102 | * with U-Boot image. |
| 103 | */ |
Semen Protsenko | d776ecf | 2016-11-16 19:19:06 +0200 | [diff] [blame] | 104 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 105 | #endif /* ifdef CONFIG_SECURE_BOOT */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 106 | |
| 107 | #define CONFIG_SPL_TEXT_BASE 0x10000000 |
| 108 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 109 | #define CONFIG_SPL_STACK 0x1001d000 |
| 110 | #define CONFIG_SPL_PAD_TO 0x1c000 |
| 111 | #define CONFIG_SYS_TEXT_BASE 0x82000000 |
| 112 | |
Tang Yuantian | 8b160bc | 2015-05-14 17:20:28 +0800 | [diff] [blame] | 113 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 114 | CONFIG_SYS_MONITOR_LEN) |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 115 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 116 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 117 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 118 | |
| 119 | #ifdef CONFIG_U_BOOT_HDR_SIZE |
| 120 | /* |
| 121 | * HDR would be appended at end of image and copied to DDR along |
| 122 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 123 | * size increases then increase this size in case of secure boot as |
| 124 | * it uses raw u-boot image instead of fit image. |
| 125 | */ |
Vinitha Pillai | 31b11c6 | 2017-02-01 18:28:53 +0530 | [diff] [blame] | 126 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 127 | #else |
Vinitha Pillai | 31b11c6 | 2017-02-01 18:28:53 +0530 | [diff] [blame] | 128 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 129 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 130 | #endif |
| 131 | |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 132 | #ifdef CONFIG_QSPI_BOOT |
Alison Wang | 2766608 | 2017-05-16 10:45:57 +0800 | [diff] [blame] | 133 | #define CONFIG_SYS_TEXT_BASE 0x40100000 |
Alison Wang | dd45cc5 | 2015-10-15 17:54:40 +0800 | [diff] [blame] | 134 | #endif |
| 135 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 136 | #ifndef CONFIG_SYS_TEXT_BASE |
Alison Wang | 4d786e8 | 2015-04-21 16:04:38 +0800 | [diff] [blame] | 137 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 138 | #endif |
| 139 | |
| 140 | #define CONFIG_NR_DRAM_BANKS 1 |
| 141 | #define PHYS_SDRAM 0x80000000 |
| 142 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
| 143 | |
| 144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
| 145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 146 | |
Alison Wang | a5494fb | 2014-12-09 17:37:49 +0800 | [diff] [blame] | 147 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
| 148 | !defined(CONFIG_QSPI_BOOT) |
Zhao Qiang | f3cc6b7 | 2014-09-26 16:25:33 +0800 | [diff] [blame] | 149 | #define CONFIG_U_QE |
Zhao Qiang | 82cd8c6 | 2017-05-25 09:47:40 +0800 | [diff] [blame] | 150 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
Zhao Qiang | f3cc6b7 | 2014-09-26 16:25:33 +0800 | [diff] [blame] | 151 | #endif |
| 152 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 153 | /* |
| 154 | * IFC Definitions |
| 155 | */ |
Alison Wang | dd45cc5 | 2015-10-15 17:54:40 +0800 | [diff] [blame] | 156 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 157 | #define CONFIG_FSL_IFC |
| 158 | #define CONFIG_SYS_FLASH_BASE 0x60000000 |
| 159 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 160 | |
| 161 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
| 162 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 163 | CSPR_PORT_SIZE_16 | \ |
| 164 | CSPR_MSEL_NOR | \ |
| 165 | CSPR_V) |
| 166 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) |
| 167 | |
| 168 | /* NOR Flash Timing Params */ |
| 169 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 170 | CSOR_NOR_TRHZ_80) |
| 171 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 172 | FTIM0_NOR_TEADC(0x5) | \ |
| 173 | FTIM0_NOR_TAVDS(0x0) | \ |
| 174 | FTIM0_NOR_TEAHC(0x5)) |
| 175 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 176 | FTIM1_NOR_TRAD_NOR(0x1A) | \ |
| 177 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 178 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 179 | FTIM2_NOR_TCH(0x4) | \ |
| 180 | FTIM2_NOR_TWP(0x1c) | \ |
| 181 | FTIM2_NOR_TWPH(0x0e)) |
| 182 | #define CONFIG_SYS_NOR_FTIM3 0 |
| 183 | |
| 184 | #define CONFIG_FLASH_CFI_DRIVER |
| 185 | #define CONFIG_SYS_FLASH_CFI |
| 186 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 187 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 188 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 189 | |
| 190 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 191 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 192 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 193 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 194 | |
| 195 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 196 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
| 197 | |
| 198 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
Yuan Yao | da17d1a | 2014-10-17 15:26:34 +0800 | [diff] [blame] | 199 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 200 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 201 | |
| 202 | /* CPLD */ |
| 203 | |
| 204 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
| 205 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 206 | |
| 207 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) |
| 208 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
| 209 | CSPR_PORT_SIZE_8 | \ |
| 210 | CSPR_MSEL_GPCM | \ |
| 211 | CSPR_V) |
| 212 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) |
| 213 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 214 | CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| 215 | CSOR_NOR_TRHZ_80) |
| 216 | |
| 217 | /* CPLD Timing parameters for IFC GPCM */ |
| 218 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
| 219 | FTIM0_GPCM_TEADC(0xf) | \ |
| 220 | FTIM0_GPCM_TEAHC(0xf)) |
| 221 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 222 | FTIM1_GPCM_TRAD(0x3f)) |
| 223 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| 224 | FTIM2_GPCM_TCH(0xf) | \ |
| 225 | FTIM2_GPCM_TWP(0xff)) |
| 226 | #define CONFIG_SYS_FPGA_FTIM3 0x0 |
| 227 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 228 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
| 229 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 230 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 231 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 232 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 233 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 234 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 235 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 236 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR |
| 237 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK |
| 238 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR |
| 239 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 |
| 240 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 |
| 241 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 |
| 242 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 |
| 243 | |
| 244 | /* |
| 245 | * Serial Port |
| 246 | */ |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 247 | #ifdef CONFIG_LPUART |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 248 | #define CONFIG_LPUART_32B_REG |
| 249 | #else |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 250 | #define CONFIG_CONS_INDEX 1 |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 251 | #define CONFIG_SYS_NS16550_SERIAL |
Bin Meng | 06229a9 | 2016-01-13 19:38:59 -0800 | [diff] [blame] | 252 | #ifndef CONFIG_DM_SERIAL |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 253 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
Bin Meng | 06229a9 | 2016-01-13 19:38:59 -0800 | [diff] [blame] | 254 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 255 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 256 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 257 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 258 | /* |
| 259 | * I2C |
| 260 | */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 261 | #define CONFIG_SYS_I2C |
| 262 | #define CONFIG_SYS_I2C_MXC |
Albert ARIBAUD \\(3ADEV\\) | eb94387 | 2015-09-21 22:43:38 +0200 | [diff] [blame] | 263 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 264 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
York Sun | f1a5216 | 2015-03-20 10:20:40 -0700 | [diff] [blame] | 265 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 266 | |
Alison Wang | af276f4 | 2014-10-17 15:26:35 +0800 | [diff] [blame] | 267 | /* EEPROM */ |
Alison Wang | af276f4 | 2014-10-17 15:26:35 +0800 | [diff] [blame] | 268 | #define CONFIG_ID_EEPROM |
| 269 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 270 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
| 271 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
| 272 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 273 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 274 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
Alison Wang | af276f4 | 2014-10-17 15:26:35 +0800 | [diff] [blame] | 275 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 276 | /* |
| 277 | * MMC |
| 278 | */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 279 | #define CONFIG_FSL_ESDHC |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 280 | |
Haikun Wang | 8cd8437 | 2015-06-27 21:46:13 +0530 | [diff] [blame] | 281 | /* SPI */ |
Alison Wang | dd45cc5 | 2015-10-15 17:54:40 +0800 | [diff] [blame] | 282 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
Haikun Wang | 8cd8437 | 2015-06-27 21:46:13 +0530 | [diff] [blame] | 283 | /* QSPI */ |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 284 | #define QSPI0_AMBA_BASE 0x40000000 |
| 285 | #define FSL_QSPI_FLASH_SIZE (1 << 24) |
| 286 | #define FSL_QSPI_FLASH_NUM 2 |
| 287 | |
Yao Yuan | ad7dbd1 | 2015-09-15 18:28:20 +0800 | [diff] [blame] | 288 | /* DSPI */ |
Yao Yuan | ad7dbd1 | 2015-09-15 18:28:20 +0800 | [diff] [blame] | 289 | #endif |
| 290 | |
Haikun Wang | 8cd8437 | 2015-06-27 21:46:13 +0530 | [diff] [blame] | 291 | /* DM SPI */ |
| 292 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) |
Haikun Wang | 8cd8437 | 2015-06-27 21:46:13 +0530 | [diff] [blame] | 293 | #define CONFIG_DM_SPI_FLASH |
| 294 | #endif |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 295 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 296 | /* |
Wang Huan | 9207219 | 2014-09-05 13:52:50 +0800 | [diff] [blame] | 297 | * Video |
| 298 | */ |
Sanchayan Maity | e15479b | 2017-04-11 11:12:09 +0530 | [diff] [blame] | 299 | #ifdef CONFIG_VIDEO_FSL_DCU_FB |
Wang Huan | 9207219 | 2014-09-05 13:52:50 +0800 | [diff] [blame] | 300 | #define CONFIG_VIDEO_LOGO |
| 301 | #define CONFIG_VIDEO_BMP_LOGO |
| 302 | |
| 303 | #define CONFIG_FSL_DCU_SII9022A |
| 304 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 |
| 305 | #define CONFIG_SYS_I2C_DVI_ADDR 0x39 |
| 306 | #endif |
| 307 | |
| 308 | /* |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 309 | * eTSEC |
| 310 | */ |
| 311 | #define CONFIG_TSEC_ENET |
| 312 | |
| 313 | #ifdef CONFIG_TSEC_ENET |
| 314 | #define CONFIG_MII |
| 315 | #define CONFIG_MII_DEFAULT_TSEC 1 |
| 316 | #define CONFIG_TSEC1 1 |
| 317 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 318 | #define CONFIG_TSEC2 1 |
| 319 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 320 | #define CONFIG_TSEC3 1 |
| 321 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 322 | |
| 323 | #define TSEC1_PHY_ADDR 2 |
| 324 | #define TSEC2_PHY_ADDR 0 |
| 325 | #define TSEC3_PHY_ADDR 1 |
| 326 | |
| 327 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 328 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 329 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 330 | |
| 331 | #define TSEC1_PHYIDX 0 |
| 332 | #define TSEC2_PHYIDX 0 |
| 333 | #define TSEC3_PHYIDX 0 |
| 334 | |
| 335 | #define CONFIG_ETHPRIME "eTSEC1" |
| 336 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 337 | #define CONFIG_PHY_ATHEROS |
| 338 | |
| 339 | #define CONFIG_HAS_ETH0 |
| 340 | #define CONFIG_HAS_ETH1 |
| 341 | #define CONFIG_HAS_ETH2 |
| 342 | #endif |
| 343 | |
Minghuan Lian | a4d6b61 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 344 | /* PCIe */ |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 345 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 346 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
Minghuan Lian | a4d6b61 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 347 | |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 348 | #ifdef CONFIG_PCI |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 349 | #define CONFIG_PCI_SCAN_SHOW |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 350 | #endif |
| 351 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 352 | #define CONFIG_CMDLINE_TAG |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 353 | |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 354 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
Mingkai Hu | 5b0df8a | 2015-10-26 19:47:41 +0800 | [diff] [blame] | 355 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 356 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
Andre Przywara | 70c7893 | 2017-02-16 01:20:19 +0000 | [diff] [blame] | 357 | #define COUNTER_FREQUENCY 12500000 |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 358 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 359 | #define CONFIG_HWCONFIG |
Zhuoyu Zhang | fe4f288 | 2015-08-17 18:55:12 +0800 | [diff] [blame] | 360 | #define HWCONFIG_BUFFER_SIZE 256 |
| 361 | |
| 362 | #define CONFIG_FSL_DEVICE_DISABLE |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 363 | |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 364 | #include <config_distro_defaults.h> |
| 365 | #define BOOT_TARGET_DEVICES(func) \ |
| 366 | func(MMC, mmc, 0) \ |
| 367 | func(USB, usb, 0) |
| 368 | #include <config_distro_bootcmd.h> |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 369 | |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 370 | #ifdef CONFIG_LPUART |
| 371 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 372 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ |
Alison Wang | ec2ab3c | 2015-10-26 14:08:28 +0800 | [diff] [blame] | 373 | "initrd_high=0xffffffff\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 374 | "fdt_high=0xffffffff\0" \ |
| 375 | "fdt_addr=0x64f00000\0" \ |
| 376 | "kernel_addr=0x65000000\0" \ |
| 377 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 378 | "scripthdraddr=0x80080000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 379 | "fdtheader_addr_r=0x80100000\0" \ |
| 380 | "kernelheader_addr_r=0x80200000\0" \ |
| 381 | "kernel_addr_r=0x81000000\0" \ |
| 382 | "fdt_addr_r=0x90000000\0" \ |
| 383 | "ramdisk_addr_r=0xa0000000\0" \ |
| 384 | "load_addr=0xa0000000\0" \ |
| 385 | "kernel_size=0x2800000\0" \ |
| 386 | BOOTENV \ |
| 387 | "boot_scripts=ls1021atwr_boot.scr\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 388 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 389 | "scan_dev_for_boot_part=" \ |
| 390 | "part list ${devtype} ${devnum} devplist; " \ |
| 391 | "env exists devplist || setenv devplist 1; " \ |
| 392 | "for distro_bootpart in ${devplist}; do " \ |
| 393 | "if fstype ${devtype} " \ |
| 394 | "${devnum}:${distro_bootpart} " \ |
| 395 | "bootfstype; then " \ |
| 396 | "run scan_dev_for_boot; " \ |
| 397 | "fi; " \ |
| 398 | "done\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 399 | "scan_dev_for_boot=" \ |
| 400 | "echo Scanning ${devtype} " \ |
| 401 | "${devnum}:${distro_bootpart}...; " \ |
| 402 | "for prefix in ${boot_prefixes}; do " \ |
| 403 | "run scan_dev_for_scripts; " \ |
| 404 | "done;" \ |
| 405 | "\0" \ |
| 406 | "boot_a_script=" \ |
| 407 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 408 | "${scriptaddr} ${prefix}${script}; " \ |
| 409 | "env exists secureboot && load ${devtype} " \ |
| 410 | "${devnum}:${distro_bootpart} " \ |
| 411 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ |
| 412 | "&& esbc_validate ${scripthdraddr};" \ |
| 413 | "source ${scriptaddr}\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 414 | "installer=load mmc 0:2 $load_addr " \ |
| 415 | "/flex_installer_arm32.itb; " \ |
| 416 | "bootm $load_addr#ls1021atwr\0" \ |
| 417 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 418 | "sf probe && sf read $load_addr " \ |
| 419 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ |
| 420 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 421 | "cp.b $kernel_addr $load_addr " \ |
| 422 | "$kernel_size && bootm $load_addr#$board\0" |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 423 | #else |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 424 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 425 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ |
Alison Wang | ec2ab3c | 2015-10-26 14:08:28 +0800 | [diff] [blame] | 426 | "initrd_high=0xffffffff\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 427 | "fdt_high=0xffffffff\0" \ |
| 428 | "fdt_addr=0x64f00000\0" \ |
| 429 | "kernel_addr=0x65000000\0" \ |
| 430 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 431 | "scripthdraddr=0x80080000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 432 | "fdtheader_addr_r=0x80100000\0" \ |
| 433 | "kernelheader_addr_r=0x80200000\0" \ |
| 434 | "kernel_addr_r=0x81000000\0" \ |
| 435 | "fdt_addr_r=0x90000000\0" \ |
| 436 | "ramdisk_addr_r=0xa0000000\0" \ |
| 437 | "load_addr=0xa0000000\0" \ |
| 438 | "kernel_size=0x2800000\0" \ |
| 439 | BOOTENV \ |
| 440 | "boot_scripts=ls1021atwr_boot.scr\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 441 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 442 | "scan_dev_for_boot_part=" \ |
| 443 | "part list ${devtype} ${devnum} devplist; " \ |
| 444 | "env exists devplist || setenv devplist 1; " \ |
| 445 | "for distro_bootpart in ${devplist}; do " \ |
| 446 | "if fstype ${devtype} " \ |
| 447 | "${devnum}:${distro_bootpart} " \ |
| 448 | "bootfstype; then " \ |
| 449 | "run scan_dev_for_boot; " \ |
| 450 | "fi; " \ |
| 451 | "done\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 452 | "scan_dev_for_boot=" \ |
| 453 | "echo Scanning ${devtype} " \ |
| 454 | "${devnum}:${distro_bootpart}...; " \ |
| 455 | "for prefix in ${boot_prefixes}; do " \ |
| 456 | "run scan_dev_for_scripts; " \ |
| 457 | "done;" \ |
| 458 | "\0" \ |
| 459 | "boot_a_script=" \ |
| 460 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 461 | "${scriptaddr} ${prefix}${script}; " \ |
| 462 | "env exists secureboot && load ${devtype} " \ |
| 463 | "${devnum}:${distro_bootpart} " \ |
| 464 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ |
| 465 | "&& esbc_validate ${scripthdraddr};" \ |
| 466 | "source ${scriptaddr}\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 467 | "installer=load mmc 0:2 $load_addr " \ |
| 468 | "/flex_installer_arm32.itb; " \ |
| 469 | "bootm $load_addr#ls1021atwr\0" \ |
| 470 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 471 | "sf probe && sf read $load_addr " \ |
| 472 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ |
| 473 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 474 | "cp.b $kernel_addr $load_addr " \ |
| 475 | "$kernel_size && bootm $load_addr#$board\0" |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 476 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 477 | |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 478 | #undef CONFIG_BOOTCOMMAND |
| 479 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 480 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ |
| 481 | "&& esbc_halt; run qspi_bootcmd;" |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 482 | #else |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 483 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ |
| 484 | "&& esbc_halt; run nor_bootcmd;" |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 485 | #endif |
| 486 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 487 | /* |
| 488 | * Miscellaneous configurable options |
| 489 | */ |
| 490 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 491 | #define CONFIG_AUTO_COMPLETE |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 492 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 493 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| 494 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| 495 | |
| 496 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 497 | |
Xiubo Li | 03d40aa | 2014-11-21 17:40:59 +0800 | [diff] [blame] | 498 | #define CONFIG_LS102XA_STREAM_ID |
| 499 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 500 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 501 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 502 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 503 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 504 | |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 505 | #ifdef CONFIG_SPL_BUILD |
| 506 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 507 | #else |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 508 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 509 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 510 | |
Alison Wang | 2766608 | 2017-05-16 10:45:57 +0800 | [diff] [blame] | 511 | #define CONFIG_SYS_QE_FW_ADDR 0x60940000 |
Zhao Qiang | f3cc6b7 | 2014-09-26 16:25:33 +0800 | [diff] [blame] | 512 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 513 | /* |
| 514 | * Environment |
| 515 | */ |
| 516 | #define CONFIG_ENV_OVERWRITE |
| 517 | |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 518 | #if defined(CONFIG_SD_BOOT) |
Alison Wang | 2766608 | 2017-05-16 10:45:57 +0800 | [diff] [blame] | 519 | #define CONFIG_ENV_OFFSET 0x300000 |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 520 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 521 | #define CONFIG_ENV_SIZE 0x20000 |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 522 | #elif defined(CONFIG_QSPI_BOOT) |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 523 | #define CONFIG_ENV_SIZE 0x2000 |
Alison Wang | 2766608 | 2017-05-16 10:45:57 +0800 | [diff] [blame] | 524 | #define CONFIG_ENV_OFFSET 0x300000 |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 525 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 526 | #else |
Alison Wang | 2766608 | 2017-05-16 10:45:57 +0800 | [diff] [blame] | 527 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 528 | #define CONFIG_ENV_SIZE 0x20000 |
| 529 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 530 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 531 | |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 532 | #define CONFIG_MISC_INIT_R |
| 533 | |
Aneesh Bansal | 962021a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 534 | #include <asm/fsl_secure_boot.h> |
Alison Wang | 13b0bb8 | 2016-01-15 15:29:32 +0800 | [diff] [blame] | 535 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 536 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 537 | #endif |