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git01.mediatek.com / filogic / uboot / 9a4fcc8b736bf1cc1cbe7e83922e025602e96e17 / . / arch / arm / cpu / armv7 / omap4 / emif.c
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Sricharan62a86502011-11-15 09:50:00 -0500[diff] [blame]1/*
2 * EMIF programming
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Aneesh V <aneesh@ti.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <asm/emif.h>
30#include <asm/arch/sys_proto.h>
31#include <asm/utils.h>
32
33#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
34u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
35u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
36u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
37#endif
38
39#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
40/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
41static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
42 .max_freq = 400000000,
43 .RL = 6,
44 .tRPab = 21,
45 .tRCD = 18,
46 .tWR = 15,
47 .tRASmin = 42,
48 .tRRD = 10,
49 .tWTRx2 = 15,
50 .tXSR = 140,
51 .tXPx2 = 15,
52 .tRFCab = 130,
53 .tRTPx2 = 15,
54 .tCKE = 3,
55 .tCKESR = 15,
56 .tZQCS = 90,
57 .tZQCL = 360,
58 .tZQINIT = 1000,
59 .tDQSCKMAXx2 = 11,
60 .tRASmax = 70,
61 .tFAW = 50
62};
63
64/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
65static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
66 .max_freq = 200000000,
67 .RL = 3,
68 .tRPab = 21,
69 .tRCD = 18,
70 .tWR = 15,
71 .tRASmin = 42,
72 .tRRD = 10,
73 .tWTRx2 = 20,
74 .tXSR = 140,
75 .tXPx2 = 15,
76 .tRFCab = 130,
77 .tRTPx2 = 15,
78 .tCKE = 3,
79 .tCKESR = 15,
80 .tZQCS = 90,
81 .tZQCL = 360,
82 .tZQINIT = 1000,
83 .tDQSCKMAXx2 = 11,
84 .tRASmax = 70,
85 .tFAW = 50
86};
87
88/*
89 * Min tCK values specified by JESD209-2
90 * Min tCK specifies the minimum duration of some AC timing parameters in terms
91 * of the number of cycles. If the calculated number of cycles based on the
92 * absolute time value is less than the min tCK value, min tCK value should
93 * be used instead. This typically happens at low frequencies.
94 */
95static const struct lpddr2_min_tck min_tck_jedec = {
96 .tRL = 3,
97 .tRP_AB = 3,
98 .tRCD = 3,
99 .tWR = 3,
100 .tRAS_MIN = 3,
101 .tRRD = 2,
102 .tWTR = 2,
103 .tXP = 2,
104 .tRTP = 2,
105 .tCKE = 3,
106 .tCKESR = 3,
107 .tFAW = 8
108};
109
110static const struct lpddr2_ac_timings const*
111 jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
112 &timings_jedec_200_mhz,
113 &timings_jedec_400_mhz
114};
115
116static const struct lpddr2_device_timings jedec_default_timings = {
117 .ac_timings = jedec_ac_timings,
118 .min_tck = &min_tck_jedec
119};
120
121void emif_get_device_timings(u32 emif_nr,
122 const struct lpddr2_device_timings **cs0_device_timings,
123 const struct lpddr2_device_timings **cs1_device_timings)
124{
125 /* Assume Identical devices on EMIF1 & EMIF2 */
126 *cs0_device_timings = &jedec_default_timings;
127 *cs1_device_timings = &jedec_default_timings;
128}
129#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */