blob: 11b80fb190ce03165ac505bf4412d485a30b4840 [file] [log] [blame]
Matthias Weisser93416c12011-03-10 21:36:32 +00001/*
2 * arch/arm/include/asm/assembler.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file contains arm architecture specific defines
11 * for the different processors.
12 *
13 * Do not include any C declarations in this file - it is included by
14 * assembler source.
15 */
16
Stefan Agnera257f2e2014-12-18 18:10:33 +010017#include <config.h>
18
Matthias Weisser93416c12011-03-10 21:36:32 +000019/*
20 * Endian independent macros for shifting bytes within registers.
21 */
22#ifndef __ARMEB__
Stefan Agnera257f2e2014-12-18 18:10:33 +010023#define lspull lsr
24#define lspush lsl
Matthias Weisser93416c12011-03-10 21:36:32 +000025#define get_byte_0 lsl #0
26#define get_byte_1 lsr #8
27#define get_byte_2 lsr #16
28#define get_byte_3 lsr #24
29#define put_byte_0 lsl #0
30#define put_byte_1 lsl #8
31#define put_byte_2 lsl #16
32#define put_byte_3 lsl #24
33#else
Stefan Agnera257f2e2014-12-18 18:10:33 +010034#define lspull lsl
35#define lspush lsr
Matthias Weisser93416c12011-03-10 21:36:32 +000036#define get_byte_0 lsr #24
37#define get_byte_1 lsr #16
38#define get_byte_2 lsr #8
39#define get_byte_3 lsl #0
40#define put_byte_0 lsl #24
41#define put_byte_1 lsl #16
42#define put_byte_2 lsl #8
43#define put_byte_3 lsl #0
44#endif
45
46/*
47 * Data preload for architectures that support it
48 */
49#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
50 defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
51 defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
52 defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
53 defined(__ARM_ARCH_7R__)
54#define PLD(code...) code
55#else
56#define PLD(code...)
57#endif
Stefan Agnera257f2e2014-12-18 18:10:33 +010058
59 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
60 .macro ret\c, reg
61#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__)
62 mov\c pc, \reg
63#else
64 .ifeqs "\reg", "lr"
65 bx\c \reg
66 .else
67 mov\c pc, \reg
68 .endif
69#endif
70 .endm
71 .endr
Matthias Weisser93416c12011-03-10 21:36:32 +000072
73/*
Stefan Agnera257f2e2014-12-18 18:10:33 +010074 * Cache aligned, used for optimized memcpy/memset
75 * In the kernel this is only enabled for Feroceon CPU's...
76 * We disable it especially for Thumb builds since those instructions
77 * are not made in a Thumb ready way...
Matthias Weisser93416c12011-03-10 21:36:32 +000078 */
Stefan Agnera257f2e2014-12-18 18:10:33 +010079#ifdef CONFIG_SYS_THUMB_BUILD
80#define CALGN(code...)
81#else
Matthias Weisser93416c12011-03-10 21:36:32 +000082#define CALGN(code...) code
Stefan Agnera257f2e2014-12-18 18:10:33 +010083#endif