| Bob Liu | 52a310c | 2012-08-16 11:10:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004-2012 Analog Devices Inc. |
| 3 | * Licensed under the ADI BSD license. |
| 4 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd |
| 5 | */ |
| 6 | |
| 7 | /* This file should be up to date with: |
| 8 | * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List |
| 9 | */ |
| 10 | |
| 11 | #if __SILICON_REVISION__ < 0 |
| 12 | # error will not work on BF609 silicon version |
| 13 | #endif |
| 14 | |
| 15 | #ifndef _MACH_ANOMALY_H_ |
| 16 | #define _MACH_ANOMALY_H_ |
| 17 | |
| 18 | /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ |
| 19 | #define ANOMALY_16000003 (1) |
| 20 | /* The EPPI Data Enable (DEN) Signal is Not Functional */ |
| 21 | #define ANOMALY_16000004 (1) |
| 22 | /* Using L1 Instruction Cache with Parity Enabled is Unreliable */ |
| 23 | #define ANOMALY_16000005 (1) |
| 24 | /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ |
| 25 | #define ANOMALY_16000006 (1) |
| 26 | /* DDR2 Memory Reads May Fail Intermittently */ |
| 27 | #define ANOMALY_16000007 (1) |
| 28 | /* Instruction Memory Stalls Can Cause IFLUSH to Fail */ |
| 29 | #define ANOMALY_16000008 (1) |
| 30 | /* TestSET Instruction Cannot Be Interrupted */ |
| 31 | #define ANOMALY_16000009 (1) |
| 32 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 33 | #define ANOMALY_16000010 (1) |
| 34 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 35 | #define ANOMALY_16000011 (1) |
| 36 | /* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */ |
| 37 | #define ANOMALY_16000012 (1) |
| 38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 39 | #define ANOMALY_16000013 (1) |
| 40 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 41 | #define ANOMALY_16000014 (1) |
| 42 | /* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */ |
| 43 | #define ANOMALY_16000015 (1) |
| 44 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 45 | #define ANOMALY_16000017 (1) |
| 46 | /* RSI Boot Cleanup Routine Does Not Clear Registers */ |
| 47 | #define ANOMALY_16000018 (1) |
| 48 | /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ |
| 49 | #define ANOMALY_16000019 (1) |
| 50 | /* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ |
| 51 | #define ANOMALY_16000020 (1) |
| 52 | /* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */ |
| 53 | #define ANOMALY_16000021 (1) |
| 54 | /* Boot Code Fails to Enable Parity Fault Detection */ |
| 55 | #define ANOMALY_16000022 (1) |
| 56 | /* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */ |
| 57 | #define ANOMALY_16000027 (1) |
| 58 | /* Interrupted Core Reads of MMRs May Cause Data Loss */ |
| 59 | #define ANOMALY_16000030 (1) |
| 60 | |
| 61 | /* Anomalies that don't exist on this proc */ |
| 62 | #define ANOMALY_05000158 (0) |
| 63 | #define ANOMALY_05000189 (0) |
| 64 | #define ANOMALY_05000198 (0) |
| 65 | #define ANOMALY_05000219 (0) |
| 66 | #define ANOMALY_05000230 (0) |
| 67 | #define ANOMALY_05000231 (0) |
| 68 | #define ANOMALY_05000244 (0) |
| 69 | #define ANOMALY_05000261 (0) |
| 70 | #define ANOMALY_05000263 (0) |
| 71 | #define ANOMALY_05000273 (0) |
| 72 | #define ANOMALY_05000274 (0) |
| 73 | #define ANOMALY_05000278 (0) |
| 74 | #define ANOMALY_05000281 (0) |
| 75 | #define ANOMALY_05000287 (0) |
| 76 | #define ANOMALY_05000311 (0) |
| 77 | #define ANOMALY_05000312 (0) |
| 78 | #define ANOMALY_05000323 (0) |
| 79 | #define ANOMALY_05000353 (1) |
| 80 | #define ANOMALY_05000363 (0) |
| 81 | #define ANOMALY_05000386 (0) |
| 82 | #define ANOMALY_05000480 (0) |
| 83 | #define ANOMALY_05000481 (1) |
| 84 | |
| 85 | /* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */ |
| 86 | #define ANOMALY_05000491 ANOMALY_16000008 |
| 87 | #define ANOMALY_05000477 ANOMALY_16000009 |
| 88 | #define ANOMALY_05000443 ANOMALY_16000010 |
| 89 | #define ANOMALY_05000461 ANOMALY_16000011 |
| 90 | #define ANOMALY_05000426 ANOMALY_16000012 |
| 91 | #define ANOMALY_05000310 ANOMALY_16000013 |
| 92 | #define ANOMALY_05000245 ANOMALY_16000014 |
| 93 | #define ANOMALY_05000074 ANOMALY_16000015 |
| 94 | #define ANOMALY_05000416 ANOMALY_16000017 |
| 95 | |
| 96 | |
| 97 | #endif |