dts/upstream/Bindings/clock/mediatek,mt7988-xfi-pll.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MT7988 XFI PLL Clock Controller

maintainers:
  - Daniel Golle <daniel@makrotopia.org>

description:
  The MediaTek XFI PLL controller provides the 156.25MHz clock for the
  Ethernet SerDes PHY from the 40MHz top_xtal clock.

properties:
  compatible:
    const: mediatek,mt7988-xfi-pll

  reg:
    maxItems: 1

  resets:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - resets
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        clock-controller@11f40000 {
            compatible = "mediatek,mt7988-xfi-pll";
            reg = <0 0x11f40000 0 0x1000>;
            resets = <&watchdog 16>;
            #clock-cells = <1>;
        };
    };