blob: 0cc675781d160db476a11fad7b99aa8cc032ac82 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc.
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020010 */
11
Tom Rinidec7ea02024-05-20 13:35:03 -060012#include <config.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020013#include <asm/mmu.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060014#include <asm/ppc.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020015
16struct fsl_e_tlb_entry tlb_table[] = {
17 /* TLB 0 - for temp stack in cache */
Tom Rini6a5dccc2022-11-16 13:10:41 -050018 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020019 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
Tom Rini6a5dccc2022-11-16 13:10:41 -050021 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020022 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
Tom Rini6a5dccc2022-11-16 13:10:41 -050024 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020025 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
Tom Rini6a5dccc2022-11-16 13:10:41 -050027 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020028 MAS3_SX|MAS3_SW|MAS3_SR, 0,
29 0, 0, BOOKE_PAGESZ_4K, 0),
30
31
32 /*
Anatolij Gustschine6f5c912008-08-15 15:42:13 +020033 * TLB 1: 64M Non-cacheable, guarded
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020034 * 0xfc000000 64M FLASH
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020035 * Out of reset this entry is only 4K.
36 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050037 SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020038 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
39 0, 1, BOOKE_PAGESZ_64M, 1),
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020040
41 /*
42 * TLB 2: 256M Non-cacheable, guarded
43 * 0x80000000 256M PCI1 MEM First half
44 */
Tom Rini56af6592022-11-16 13:10:33 -050045 SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020046 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
47 0, 2, BOOKE_PAGESZ_256M, 1),
48
49 /*
50 * TLB 3: 256M Non-cacheable, guarded
51 * 0x90000000 256M PCI1 MEM Second half
52 */
Tom Rini56af6592022-11-16 13:10:33 -050053 SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020054 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 3, BOOKE_PAGESZ_256M, 1),
56
Tom Rini6a5dccc2022-11-16 13:10:41 -050057#if defined(CFG_SYS_FPGA_BASE)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020058 /*
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020059 * TLB 4: 1M Non-cacheable, guarded
60 * 0xc0000000 1M FPGA and NAND
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020061 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050062 SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020063 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020064 0, 4, BOOKE_PAGESZ_1M, 1),
65#endif
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020066
67 /*
Anatolij Gustschine6f5c912008-08-15 15:42:13 +020068 * TLB 5: 64M Non-cacheable, guarded
69 * 0xc8000000 16M LIME GDC framebuffer
70 * 0xc9fc0000 256K LIME GDC MMIO
71 * (0xcbfc0000 256K LIME GDC MMIO)
72 * MMIO is relocatable and could be at 0xcbfc0000
73 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050074 SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE,
Anatolij Gustschine6f5c912008-08-15 15:42:13 +020075 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, 5, BOOKE_PAGESZ_64M, 1),
77
78 /*
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020079 * TLB 6: 64M Non-cacheable, guarded
80 * 0xe000_0000 1M CCSRBAR
81 * 0xe200_0000 16M PCI1 IO
82 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050083 SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020084 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85 0, 6, BOOKE_PAGESZ_64M, 1),
86
Anatolij Gustschina49dccd2008-11-13 18:08:57 +010087#if !defined(CONFIG_SPD_EEPROM)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020088 /*
89 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
90 * 0x00000000 512M DDR System memory
91 * Without SPD EEPROM configured DDR, this must be setup manually.
92 * Make sure the TLB count at the top of this table is correct.
93 * Likely it needs to be increased by two for these entries.
94 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050095 SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020096 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
97 0, 7, BOOKE_PAGESZ_256M, 1),
98
Tom Rini6a5dccc2022-11-16 13:10:41 -050099 SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000,
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
101 0, 8, BOOKE_PAGESZ_256M, 1),
Anatolij Gustschina49dccd2008-11-13 18:08:57 +0100102#endif
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200103};
104
105int num_tlb_entries = ARRAY_SIZE(tlb_table);