Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2008 |
| 4 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
| 5 | * |
| 6 | * Copyright 2008 Freescale Semiconductor, Inc. |
| 7 | * |
| 8 | * (C) Copyright 2000 |
| 9 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 10 | */ |
| 11 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 12 | #include <config.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 13 | #include <asm/mmu.h> |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 14 | #include <asm/ppc.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 15 | |
| 16 | struct fsl_e_tlb_entry tlb_table[] = { |
| 17 | /* TLB 0 - for temp stack in cache */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 18 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 19 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 20 | 0, 0, BOOKE_PAGESZ_4K, 0), |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 21 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 22 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 23 | 0, 0, BOOKE_PAGESZ_4K, 0), |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 24 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 25 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 26 | 0, 0, BOOKE_PAGESZ_4K, 0), |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 27 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 28 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 29 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 30 | |
| 31 | |
| 32 | /* |
Anatolij Gustschin | e6f5c91 | 2008-08-15 15:42:13 +0200 | [diff] [blame] | 33 | * TLB 1: 64M Non-cacheable, guarded |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 34 | * 0xfc000000 64M FLASH |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 35 | * Out of reset this entry is only 4K. |
| 36 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 37 | SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 38 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 39 | 0, 1, BOOKE_PAGESZ_64M, 1), |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * TLB 2: 256M Non-cacheable, guarded |
| 43 | * 0x80000000 256M PCI1 MEM First half |
| 44 | */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 45 | SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 46 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 47 | 0, 2, BOOKE_PAGESZ_256M, 1), |
| 48 | |
| 49 | /* |
| 50 | * TLB 3: 256M Non-cacheable, guarded |
| 51 | * 0x90000000 256M PCI1 MEM Second half |
| 52 | */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 53 | SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 54 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 55 | 0, 3, BOOKE_PAGESZ_256M, 1), |
| 56 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 57 | #if defined(CFG_SYS_FPGA_BASE) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 58 | /* |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 59 | * TLB 4: 1M Non-cacheable, guarded |
| 60 | * 0xc0000000 1M FPGA and NAND |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 61 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 62 | SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 63 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 64 | 0, 4, BOOKE_PAGESZ_1M, 1), |
| 65 | #endif |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 66 | |
| 67 | /* |
Anatolij Gustschin | e6f5c91 | 2008-08-15 15:42:13 +0200 | [diff] [blame] | 68 | * TLB 5: 64M Non-cacheable, guarded |
| 69 | * 0xc8000000 16M LIME GDC framebuffer |
| 70 | * 0xc9fc0000 256K LIME GDC MMIO |
| 71 | * (0xcbfc0000 256K LIME GDC MMIO) |
| 72 | * MMIO is relocatable and could be at 0xcbfc0000 |
| 73 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 74 | SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE, |
Anatolij Gustschin | e6f5c91 | 2008-08-15 15:42:13 +0200 | [diff] [blame] | 75 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 76 | 0, 5, BOOKE_PAGESZ_64M, 1), |
| 77 | |
| 78 | /* |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 79 | * TLB 6: 64M Non-cacheable, guarded |
| 80 | * 0xe000_0000 1M CCSRBAR |
| 81 | * 0xe200_0000 16M PCI1 IO |
| 82 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 83 | SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 84 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 85 | 0, 6, BOOKE_PAGESZ_64M, 1), |
| 86 | |
Anatolij Gustschin | a49dccd | 2008-11-13 18:08:57 +0100 | [diff] [blame] | 87 | #if !defined(CONFIG_SPD_EEPROM) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 88 | /* |
| 89 | * TLB 7+8: 512M DDR, cache disabled (needed for memory test) |
| 90 | * 0x00000000 512M DDR System memory |
| 91 | * Without SPD EEPROM configured DDR, this must be setup manually. |
| 92 | * Make sure the TLB count at the top of this table is correct. |
| 93 | * Likely it needs to be increased by two for these entries. |
| 94 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 95 | SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 96 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 97 | 0, 7, BOOKE_PAGESZ_256M, 1), |
| 98 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 99 | SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 100 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 101 | 0, 8, BOOKE_PAGESZ_256M, 1), |
Anatolij Gustschin | a49dccd | 2008-11-13 18:08:57 +0100 | [diff] [blame] | 102 | #endif |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |