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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stelian Pop0bf5cad2008-05-08 18:52:25 +02002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02005 * Lead Tech Design <www.leadtechdesign.com>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02006 */
7
Tom Rinidec7ea02024-05-20 13:35:03 -06008#include <config.h>
Wenyou Yangde5793e2017-04-18 15:28:29 +08009#include <debug_uart.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070010#include <init.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070011#include <vsprintf.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Xu, Hong0c0fb212011-08-01 03:56:53 +000013#include <asm/io.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060014#include <asm/mach-types.h>
Stelian Pop0bf5cad2008-05-08 18:52:25 +020015#include <asm/arch/at91sam9rl.h>
16#include <asm/arch/at91sam9rl_matrix.h>
17#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +010018#include <asm/arch/at91_common.h>
Stelian Pop0bf5cad2008-05-08 18:52:25 +020019#include <asm/arch/at91_rstc.h>
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020020#include <asm/arch/clk.h>
Stelian Pop0bf5cad2008-05-08 18:52:25 +020021#include <asm/arch/gpio.h>
Xu, Hong0c0fb212011-08-01 03:56:53 +000022
Stelian Popcea5c532008-05-08 14:52:32 +020023#include <atmel_lcdc.h>
Stelian Pop0bf5cad2008-05-08 18:52:25 +020024
25DECLARE_GLOBAL_DATA_PTR;
26
27/* ------------------------------------------------------------------------- */
28/*
29 * Miscelaneous platform dependent initialisations
30 */
31
Stelian Pop0bf5cad2008-05-08 18:52:25 +020032#ifdef CONFIG_CMD_NAND
33static void at91sam9rlek_nand_hw_init(void)
34{
Xu, Hong0c0fb212011-08-01 03:56:53 +000035 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
Stelian Pop0bf5cad2008-05-08 18:52:25 +020037 unsigned long csa;
38
39 /* Enable CS3 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000040 csa = readl(&matrix->ebicsa);
41 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
42
43 writel(csa, &matrix->ebicsa);
Stelian Pop0bf5cad2008-05-08 18:52:25 +020044
45 /* Configure SMC CS3 for NAND/SmartMedia */
Xu, Hong0c0fb212011-08-01 03:56:53 +000046 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
48 &smc->cs[3].setup);
49 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
51 &smc->cs[3].pulse);
52 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
53 &smc->cs[3].cycle);
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#ifdef CONFIG_SYS_NAND_DBW_16
Xu, Hong0c0fb212011-08-01 03:56:53 +000057 AT91_SMC_MODE_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#else /* CONFIG_SYS_NAND_DBW_8 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000059 AT91_SMC_MODE_DBW_8 |
Stelian Pop0bf5cad2008-05-08 18:52:25 +020060#endif
Xu, Hong0c0fb212011-08-01 03:56:53 +000061 AT91_SMC_MODE_TDF_CYCLE(2),
62 &smc->cs[3].mode);
Stelian Pop0bf5cad2008-05-08 18:52:25 +020063
Wenyou Yang78f89762016-02-03 10:16:50 +080064 at91_periph_clk_enable(ATMEL_ID_PIOD);
Stelian Pop0bf5cad2008-05-08 18:52:25 +020065
66 /* Configure RDY/BSY */
Tom Rinib4213492022-11-12 17:36:51 -050067 at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
Stelian Pop0bf5cad2008-05-08 18:52:25 +020068
69 /* Enable NandFlash */
Tom Rinib4213492022-11-12 17:36:51 -050070 at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop0bf5cad2008-05-08 18:52:25 +020071
72 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
73 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
74}
75#endif
76
Wenyou Yangde5793e2017-04-18 15:28:29 +080077#ifdef CONFIG_DEBUG_UART_BOARD_INIT
78void board_debug_uart_init(void)
79{
80 at91_seriald_hw_init();
81}
82#endif
83
84#ifdef CONFIG_BOARD_EARLY_INIT_F
Xu, Hong0c0fb212011-08-01 03:56:53 +000085int board_early_init_f(void)
86{
Xu, Hong0c0fb212011-08-01 03:56:53 +000087 return 0;
88}
Wenyou Yangde5793e2017-04-18 15:28:29 +080089#endif
Stelian Popcea5c532008-05-08 14:52:32 +020090
Stelian Pop0bf5cad2008-05-08 18:52:25 +020091int board_init(void)
92{
Stelian Pop0bf5cad2008-05-08 18:52:25 +020093 /* arch number of AT91SAM9RLEK-Board */
94 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
95 /* adress of boot parameters */
Tom Rinibb4dd962022-11-16 13:10:37 -050096 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
Stelian Pop0bf5cad2008-05-08 18:52:25 +020097
Stelian Pop0bf5cad2008-05-08 18:52:25 +020098#ifdef CONFIG_CMD_NAND
99 at91sam9rlek_nand_hw_init();
100#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200101 return 0;
102}
103
104int dram_init(void)
105{
Xu, Hong0c0fb212011-08-01 03:56:53 +0000106 gd->ram_size = get_ram_size(
Tom Rinibb4dd962022-11-16 13:10:37 -0500107 (void *)CFG_SYS_SDRAM_BASE,
108 CFG_SYS_SDRAM_SIZE);
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200109 return 0;
110}