blob: e8a7830fc05690aad234e5647b13020715c0f7ef [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Guinota35cb4c2011-11-21 19:25:47 +05302/*
3 * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
Simon Guinota35cb4c2011-11-21 19:25:47 +05304 */
5
Simon Guinota35cb4c2011-11-21 19:25:47 +05306#include <i2c.h>
7#include <miiphy.h>
8
9#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
10
Simon Guinot13c5ae62012-09-06 10:51:42 +000011#define MII_MARVELL_PHY_PAGE 22
12
Simon Guinota35cb4c2011-11-21 19:25:47 +053013#define MV88E1116_LED_FCTRL_REG 10
14#define MV88E1116_CPRSP_CR3_REG 21
15#define MV88E1116_MAC_CTRL_REG 21
Simon Guinota35cb4c2011-11-21 19:25:47 +053016#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
17#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
18
Simon Guinot0473b682012-06-05 13:16:00 +000019void mv_phy_88e1116_init(const char *name, u16 phyaddr)
Simon Guinota35cb4c2011-11-21 19:25:47 +053020{
21 u16 reg;
Simon Guinota35cb4c2011-11-21 19:25:47 +053022
23 if (miiphy_set_current_dev(name))
24 return;
25
Simon Guinota35cb4c2011-11-21 19:25:47 +053026 /*
27 * Enable RGMII delay on Tx and Rx for CPU port
28 * Ref: sec 4.7.2 of chip datasheet
29 */
Simon Guinot13c5ae62012-09-06 10:51:42 +000030 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
Simon Guinot0473b682012-06-05 13:16:00 +000031 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
Simon Guinota35cb4c2011-11-21 19:25:47 +053032 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
Simon Guinot0473b682012-06-05 13:16:00 +000033 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
Simon Guinot13c5ae62012-09-06 10:51:42 +000034 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
Simon Guinota35cb4c2011-11-21 19:25:47 +053035
Simon Guinot0473b682012-06-05 13:16:00 +000036 if (miiphy_reset(name, phyaddr) == 0)
37 printf("88E1116 Initialized on %s\n", name);
Simon Guinota35cb4c2011-11-21 19:25:47 +053038}
Simon Guinot13c5ae62012-09-06 10:51:42 +000039
40void mv_phy_88e1318_init(const char *name, u16 phyaddr)
41{
42 u16 reg;
43
44 if (miiphy_set_current_dev(name))
45 return;
46
47 /*
48 * Set control mode 4 for LED[0].
49 */
50 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
51 miiphy_read(name, phyaddr, 16, &reg);
52 reg |= 0xf;
53 miiphy_write(name, phyaddr, 16, reg);
54
55 /*
56 * Enable RGMII delay on Tx and Rx for CPU port
57 * Ref: sec 4.7.2 of chip datasheet
58 */
59 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
60 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
61 reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
62 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
63 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
64
65 if (miiphy_reset(name, phyaddr) == 0)
66 printf("88E1318 Initialized on %s\n", name);
67}
Simon Guinota35cb4c2011-11-21 19:25:47 +053068#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
69
70#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
71int lacie_read_mac_address(uchar *mac_addr)
72{
73 int ret;
74 ushort version;
75
76 /* I2C-0 for on-board EEPROM */
77 i2c_set_bus_num(0);
78
79 /* Check layout version for EEPROM data */
80 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
81 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
82 (uchar *) &version, 2);
83 if (ret != 0) {
84 printf("Error: failed to read I2C EEPROM @%02x\n",
85 CONFIG_SYS_I2C_EEPROM_ADDR);
86 return ret;
87 }
88 version = be16_to_cpu(version);
89 if (version < 1 || version > 3) {
90 printf("Error: unknown version %d for EEPROM data\n",
91 version);
92 return -1;
93 }
94
95 /* Read Ethernet MAC address from EEPROM */
96 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
97 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
98 if (ret != 0)
99 printf("Error: failed to read I2C EEPROM @%02x\n",
100 CONFIG_SYS_I2C_EEPROM_ADDR);
101 return ret;
102}
103#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */