Michal Simek | b513bcd | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) |
| 4 | */ |
| 5 | |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 6 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 7 | #include <init.h> |
Michal Simek | b513bcd | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 8 | #include <asm/armv7_mpu.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 9 | #include <asm/global_data.h> |
Michal Simek | b513bcd | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 10 | |
| 11 | DECLARE_GLOBAL_DATA_PTR; |
| 12 | |
| 13 | struct mpu_region_config region_config[] = { |
Michal Simek | 3efcbe5 | 2020-09-14 16:33:46 +0200 | [diff] [blame] | 14 | { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, |
| 15 | SHARED_WRITE_BUFFERED, REGION_4GB }, |
| 16 | { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, |
Michal Simek | b513bcd | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 17 | O_I_WB_RD_WR_ALLOC, REGION_1GB }, |
| 18 | }; |
| 19 | |
| 20 | int arch_cpu_init(void) |
| 21 | { |
| 22 | gd->cpu_clk = CONFIG_CPU_FREQ_HZ; |
| 23 | |
Michal Simek | 3efcbe5 | 2020-09-14 16:33:46 +0200 | [diff] [blame] | 24 | setup_mpu_regions(region_config, ARRAY_SIZE(region_config)); |
Michal Simek | b513bcd | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 25 | |
| 26 | return 0; |
| 27 | } |
| 28 | |
| 29 | /* |
| 30 | * Perform the low-level reset. |
| 31 | */ |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 32 | void reset_cpu(void) |
Michal Simek | b513bcd | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 33 | { |
| 34 | while (1) |
| 35 | ; |
| 36 | } |