blob: 9a912dd5bd7cd30fccf42b33878f5b3444b0c35b [file] [log] [blame]
Michal Simekb513bcd2018-04-12 17:39:46 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
4 */
5
Simon Glassafb02152019-12-28 10:45:01 -07006#include <cpu_func.h>
Simon Glass97589732020-05-10 11:40:02 -06007#include <init.h>
Michal Simekb513bcd2018-04-12 17:39:46 +02008#include <asm/armv7_mpu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Michal Simekb513bcd2018-04-12 17:39:46 +020010
11DECLARE_GLOBAL_DATA_PTR;
12
13struct mpu_region_config region_config[] = {
Michal Simek3efcbe52020-09-14 16:33:46 +020014 { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
15 SHARED_WRITE_BUFFERED, REGION_4GB },
16 { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
Michal Simekb513bcd2018-04-12 17:39:46 +020017 O_I_WB_RD_WR_ALLOC, REGION_1GB },
18};
19
20int arch_cpu_init(void)
21{
22 gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
23
Michal Simek3efcbe52020-09-14 16:33:46 +020024 setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
Michal Simekb513bcd2018-04-12 17:39:46 +020025
26 return 0;
27}
28
29/*
30 * Perform the low-level reset.
31 */
Harald Seiler6f14d5f2020-12-15 16:47:52 +010032void reset_cpu(void)
Michal Simekb513bcd2018-04-12 17:39:46 +020033{
34 while (1)
35 ;
36}