| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Andre Renaud | ff38e7e | 2016-05-05 07:28:05 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Google, Inc |
| 4 | * Written by Simon Glass <sjg@chromium.org> |
| Andre Renaud | ff38e7e | 2016-05-05 07:28:05 -0600 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef AT91_SCK_H |
| 8 | #define AT91_SCK_H |
| 9 | |
| 10 | /* |
| 11 | * SCKCR flags |
| 12 | */ |
| 13 | #define AT91SAM9G45_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ |
| 14 | #define AT91SAM9G45_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ |
| 15 | #define AT91SAM9G45_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ |
| 16 | #define AT91SAM9G45_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ |
| 17 | #define AT91SAM9G45_SCKCR_OSCSEL_RC (0 << 3) |
| 18 | #define AT91SAM9G45_SCKCR_OSCSEL_32 (1 << 3) |
| 19 | |
| 20 | #endif |