| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 2 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 3 | CONFIG_ARCH_ZYNQ=y |
| 4 | CONFIG_SYS_TEXT_BASE=0x4000000 |
| Tom Rini | c9285bf | 2019-04-29 15:54:04 -0400 | [diff] [blame] | 5 | CONFIG_SPL_STACK_R_ADDR=0x200000 |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 6 | CONFIG_SPL=y |
| 7 | CONFIG_DEBUG_UART_BASE=0xe0001000 |
| 8 | CONFIG_DEBUG_UART_CLOCK=50000000 |
| 9 | CONFIG_IDENT_STRING=" Xilinx Zynq DLC20 Rev1.0" |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 10 | CONFIG_DEBUG_UART=y |
| 11 | CONFIG_DISTRO_DEFAULTS=y |
| 12 | CONFIG_FIT=y |
| 13 | CONFIG_FIT_SIGNATURE=y |
| 14 | CONFIG_FIT_VERBOSE=y |
| 15 | CONFIG_IMAGE_FORMAT_LEGACY=y |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 16 | CONFIG_BOARD_EARLY_INIT_F=y |
| 17 | CONFIG_SPL_STACK_R=y |
| 18 | CONFIG_SPL_OS_BOOT=y |
| 19 | CONFIG_SPL_SPI_LOAD=y |
| 20 | CONFIG_SYS_PROMPT="Zynq> " |
| 21 | CONFIG_CMD_THOR_DOWNLOAD=y |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 22 | CONFIG_CMD_DFU=y |
| 23 | # CONFIG_CMD_FLASH is not set |
| 24 | CONFIG_CMD_FPGA_LOADBP=y |
| 25 | CONFIG_CMD_FPGA_LOADFS=y |
| 26 | CONFIG_CMD_FPGA_LOADMK=y |
| 27 | CONFIG_CMD_FPGA_LOADP=y |
| 28 | CONFIG_CMD_GPIO=y |
| 29 | CONFIG_CMD_I2C=y |
| 30 | CONFIG_CMD_MMC=y |
| 31 | CONFIG_CMD_SF=y |
| 32 | CONFIG_CMD_USB=y |
| 33 | # CONFIG_CMD_SETEXPR is not set |
| 34 | CONFIG_CMD_TFTPPUT=y |
| 35 | CONFIG_CMD_CACHE=y |
| 36 | CONFIG_CMD_EXT4_WRITE=y |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 37 | CONFIG_DEFAULT_DEVICE_TREE="zynq-dlc20-rev1.0" |
| 38 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 39 | CONFIG_NET_RANDOM_ETHADDR=y |
| 40 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 41 | CONFIG_DFU_MMC=y |
| 42 | CONFIG_DFU_RAM=y |
| 43 | CONFIG_FPGA_XILINX=y |
| 44 | CONFIG_FPGA_ZYNQPL=y |
| 45 | CONFIG_DM_GPIO=y |
| Michal Simek | 2a6fafb | 2019-01-22 14:43:04 +0100 | [diff] [blame] | 46 | CONFIG_DM_I2C=y |
| 47 | CONFIG_SYS_I2C_CADENCE=y |
| 48 | CONFIG_MISC=y |
| 49 | CONFIG_I2C_EEPROM=y |
| 50 | CONFIG_SYS_I2C_EEPROM_ADDR=0x0 |
| 51 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 52 | CONFIG_MMC_SDHCI=y |
| 53 | CONFIG_MMC_SDHCI_ZYNQ=y |
| 54 | CONFIG_SPI_FLASH=y |
| Patrick Delaunay | 0df8104 | 2019-02-27 15:20:36 +0100 | [diff] [blame] | 55 | CONFIG_SF_DEFAULT_SPEED=30000000 |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 56 | CONFIG_SPI_FLASH_STMICRO=y |
| 57 | CONFIG_SPI_FLASH_WINBOND=y |
| 58 | CONFIG_PHY_REALTEK=y |
| 59 | CONFIG_MII=y |
| 60 | CONFIG_ZYNQ_GEM=y |
| 61 | CONFIG_DEBUG_UART_ZYNQ=y |
| 62 | CONFIG_DEBUG_UART_ANNOUNCE=y |
| 63 | CONFIG_ZYNQ_SERIAL=y |
| 64 | CONFIG_ZYNQ_QSPI=y |
| 65 | CONFIG_USB=y |
| 66 | CONFIG_USB_EHCI_HCD=y |
| 67 | CONFIG_USB_ULPI_VIEWPORT=y |
| 68 | CONFIG_USB_ULPI=y |
| Michal Simek | 4e2f4df | 2018-09-13 08:44:02 +0200 | [diff] [blame] | 69 | CONFIG_USB_GADGET=y |
| 70 | CONFIG_USB_GADGET_MANUFACTURER="Xilinx" |
| 71 | CONFIG_USB_GADGET_VENDOR_NUM=0x03fd |
| 72 | CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 |
| 73 | CONFIG_CI_UDC=y |
| 74 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 75 | CONFIG_USB_FUNCTION_THOR=y |