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git01.mediatek.com / filogic / uboot / 99b0d2ec79f52671d5f8eabd6c32a382871a4364 / . / include / configs / mx6sabresd.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Fabio Estevam77e62892012-09-13 03:18:20 +0000[diff] [blame]2/*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 *
5 * Configuration settings for the Freescale i.MX6Q SabreSD board.
Fabio Estevam77e62892012-09-13 03:18:20 +0000[diff] [blame]6 */
7
Fabio Estevamc1239082017-06-01 12:59:52 -0300[diff] [blame]8#ifndef __MX6SABRESD_CONFIG_H
9#define __MX6SABRESD_CONFIG_H
Fabio Estevam77e62892012-09-13 03:18:20 +0000[diff] [blame]10
John Tobias7706eae2014-11-12 14:27:44 -0800[diff] [blame]11#ifdef CONFIG_SPL
John Tobias7706eae2014-11-12 14:27:44 -0800[diff] [blame]12#include "imx6_spl.h"
13#endif
14
Fabio Estevam77e62892012-09-13 03:18:20 +0000[diff] [blame]15#define CONFIG_MACH_TYPE 3980
Fabio Estevamc5ca8972012-09-24 08:09:32 +0000[diff] [blame]16#define CONFIG_MXC_UART_BASE UART1_BASE
Simon Glass4694a742016-10-17 20:12:39 -0600[diff] [blame]17#define CONSOLE_DEV "ttymxc0"
Fabio Estevam77e62892012-09-13 03:18:20 +0000[diff] [blame]18
Pierre Aubertec10aed2013-06-04 09:00:15 +0200[diff] [blame]19#include "mx6sabre_common.h"
Otavio Salvador1c0b9be2012-09-26 11:37:01 +0000[diff] [blame]20
Diego Dorta466016e2016-10-11 11:09:27 -0300[diff] [blame]21/* Falcon Mode */
Tom Rini133b2e22017-01-20 19:55:53 -0500[diff] [blame]22#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
23#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
Diego Dorta466016e2016-10-11 11:09:27 -0300[diff] [blame]24#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
Diego Dorta466016e2016-10-11 11:09:27 -0300[diff] [blame]25
26/* Falcon Mode - MMC support: args@1MB kernel@2MB */
27#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
28#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
29#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
30
Shawn Guo7e5e8332012-12-30 14:14:59 +0000[diff] [blame]31#define CONFIG_SYS_FSL_USDHC_NUM 3
Shawn Guo7e5e8332012-12-30 14:14:59 +0000[diff] [blame]32
Marek Vasut0e99f012014-03-23 22:45:41 +0100[diff] [blame]33#ifdef CONFIG_CMD_PCI
Marek Vasut0e99f012014-03-23 22:45:41 +0100[diff] [blame]34#define CONFIG_PCI_SCAN_SHOW
35#define CONFIG_PCIE_IMX
36#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
37#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
38#endif
39
Fabio Estevamba92ad62014-05-09 13:15:42 -0300[diff] [blame]40/* I2C Configs */
Simon Glass0529b592021-07-10 21:14:32 -0600[diff] [blame]41#define CONFIG_SYS_I2C_LEGACY
Fabio Estevamba92ad62014-05-09 13:15:42 -0300[diff] [blame]42#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200[diff] [blame]43#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
44#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -0700[diff] [blame]45#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Fabio Estevamba92ad62014-05-09 13:15:42 -0300[diff] [blame]46#define CONFIG_SYS_I2C_SPEED 100000
47
48/* PMIC */
49#define CONFIG_POWER
50#define CONFIG_POWER_I2C
51#define CONFIG_POWER_PFUZE100
52#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
53
Peng Fanc9498fa2014-12-02 09:55:27 +0800[diff] [blame]54/* USB Configs */
Peng Fanc9498fa2014-12-02 09:55:27 +0800[diff] [blame]55#ifdef CONFIG_CMD_USB
Peng Fanc9498fa2014-12-02 09:55:27 +0800[diff] [blame]56#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Peng Fanc9498fa2014-12-02 09:55:27 +0800[diff] [blame]57#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
58#define CONFIG_MXC_USB_FLAGS 0
59#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
60#endif
61
Fabio Estevamc1239082017-06-01 12:59:52 -0300[diff] [blame]62#endif /* __MX6SABRESD_CONFIG_H */