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git01.mediatek.com / filogic / uboot / 9987846f4bc4bbebd26f011ea7a40174c9efdbd8 / . / arch / arm / include / asm / arch-imx8m / clock_imx8mm.h
blob: 305514a4eccc5b3ee948a556a1140d8391241918 [file] [log] [blame]
Peng Fan99878462019-08-27 06:25:51 +0000[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
9#define _ASM_ARCH_IMX8MM_CLOCK_H
10
11#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
12 { \
13 .rate = (_rate), \
14 .mdiv = (_m), \
15 .pdiv = (_p), \
16 .sdiv = (_s), \
17 .kdiv = (_k), \
18 }
19
20#define LOCK_STATUS BIT(31)
21#define LOCK_SEL_MASK BIT(29)
22#define CLKE_MASK BIT(11)
23#define RST_MASK BIT(9)
24#define BYPASS_MASK BIT(4)
25#define MDIV_SHIFT 12
26#define MDIV_MASK GENMASK(21, 12)
27#define PDIV_SHIFT 4
28#define PDIV_MASK GENMASK(9, 4)
29#define SDIV_SHIFT 0
30#define SDIV_MASK GENMASK(2, 0)
31#define KDIV_SHIFT 0
32#define KDIV_MASK GENMASK(15, 0)
33
34struct imx_int_pll_rate_table {
35 u32 rate;
36 int mdiv;
37 int pdiv;
38 int sdiv;
39 int kdiv;
40};
41
42enum pll_clocks {
43 ANATOP_ARM_PLL,
44 ANATOP_VPU_PLL,
45 ANATOP_GPU_PLL,
46 ANATOP_SYSTEM_PLL1,
47 ANATOP_SYSTEM_PLL2,
48 ANATOP_SYSTEM_PLL3,
49 ANATOP_AUDIO_PLL1,
50 ANATOP_AUDIO_PLL2,
51 ANATOP_VIDEO_PLL,
52 ANATOP_DRAM_PLL,
53};
54
55enum clk_root_index {
56 ARM_A53_CLK_ROOT = 0,
57 ARM_M4_CLK_ROOT = 1,
58 VPU_A53_CLK_ROOT = 2,
59 GPU3D_CLK_ROOT = 3,
60 GPU2D_CLK_ROOT = 4,
61 MAIN_AXI_CLK_ROOT = 16,
62 ENET_AXI_CLK_ROOT = 17,
63 NAND_USDHC_BUS_CLK_ROOT = 18,
64 VPU_BUS_CLK_ROOT = 19,
65 DISPLAY_AXI_CLK_ROOT = 20,
66 DISPLAY_APB_CLK_ROOT = 21,
67 DISPLAY_RTRM_CLK_ROOT = 22,
68 USB_BUS_CLK_ROOT = 23,
69 GPU_AXI_CLK_ROOT = 24,
70 GPU_AHB_CLK_ROOT = 25,
71 NOC_CLK_ROOT = 26,
72 NOC_APB_CLK_ROOT = 27,
73 AHB_CLK_ROOT = 32,
74 IPG_CLK_ROOT = 33,
75 AUDIO_AHB_CLK_ROOT = 34,
76 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
77 DRAM_SEL_CFG = 48,
78 CORE_SEL_CFG = 49,
79 DRAM_ALT_CLK_ROOT = 64,
80 DRAM_APB_CLK_ROOT = 65,
81 VPU_G1_CLK_ROOT = 66,
82 VPU_G2_CLK_ROOT = 67,
83 DISPLAY_DTRC_CLK_ROOT = 68,
84 DISPLAY_DC8000_CLK_ROOT = 69,
85 PCIE_CTRL_CLK_ROOT = 70,
86 PCIE_PHY_CLK_ROOT = 71,
87 PCIE_AUX_CLK_ROOT = 72,
88 DC_PIXEL_CLK_ROOT = 73,
89 LCDIF_PIXEL_CLK_ROOT = 74,
90 SAI1_CLK_ROOT = 75,
91 SAI2_CLK_ROOT = 76,
92 SAI3_CLK_ROOT = 77,
93 SAI4_CLK_ROOT = 78,
94 SAI5_CLK_ROOT = 79,
95 SAI6_CLK_ROOT = 80,
96 SPDIF1_CLK_ROOT = 81,
97 SPDIF2_CLK_ROOT = 82,
98 ENET_REF_CLK_ROOT = 83,
99 ENET_TIMER_CLK_ROOT = 84,
100 ENET_PHY_REF_CLK_ROOT = 85,
101 NAND_CLK_ROOT = 86,
102 QSPI_CLK_ROOT = 87,
103 USDHC1_CLK_ROOT = 88,
104 USDHC2_CLK_ROOT = 89,
105 I2C1_CLK_ROOT = 90,
106 I2C2_CLK_ROOT = 91,
107 I2C3_CLK_ROOT = 92,
108 I2C4_CLK_ROOT = 93,
109 UART1_CLK_ROOT = 94,
110 UART2_CLK_ROOT = 95,
111 UART3_CLK_ROOT = 96,
112 UART4_CLK_ROOT = 97,
113 USB_CORE_REF_CLK_ROOT = 98,
114 USB_PHY_REF_CLK_ROOT = 99,
115 GIC_CLK_ROOT = 100,
116 ECSPI1_CLK_ROOT = 101,
117 ECSPI2_CLK_ROOT = 102,
118 PWM1_CLK_ROOT = 103,
119 PWM2_CLK_ROOT = 104,
120 PWM3_CLK_ROOT = 105,
121 PWM4_CLK_ROOT = 106,
122 GPT1_CLK_ROOT = 107,
123 GPT2_CLK_ROOT = 108,
124 GPT3_CLK_ROOT = 109,
125 GPT4_CLK_ROOT = 110,
126 GPT5_CLK_ROOT = 111,
127 GPT6_CLK_ROOT = 112,
128 TRACE_CLK_ROOT = 113,
129 WDOG_CLK_ROOT = 114,
130 WRCLK_CLK_ROOT = 115,
131 IPP_DO_CLKO1 = 116,
132 IPP_DO_CLKO2 = 117,
133 MIPI_DSI_CORE_CLK_ROOT = 118,
134 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
135 MIPI_DSI_DBI_CLK_ROOT = 120,
136 USDHC3_CLK_ROOT = 121,
137 MIPI_CSI1_CORE_CLK_ROOT = 122,
138 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
139 MIPI_CSI1_ESC_CLK_ROOT = 124,
140 MIPI_CSI2_CORE_CLK_ROOT = 125,
141 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
142 MIPI_CSI2_ESC_CLK_ROOT = 127,
143 PCIE2_CTRL_CLK_ROOT = 128,
144 PCIE2_PHY_CLK_ROOT = 129,
145 PCIE2_AUX_CLK_ROOT = 130,
146 ECSPI3_CLK_ROOT = 131,
147 PDM_CLK_ROOT = 132,
148 VPU_H1_CLK_ROOT = 133,
149 CLK_ROOT_MAX,
150};
151
152enum clk_root_src {
153 OSC_24M_CLK,
154 ARM_PLL_CLK,
155 DRAM_PLL1_CLK,
156 VIDEO_PLL2_CLK,
157 VPU_PLL_CLK,
158 GPU_PLL_CLK,
159 SYSTEM_PLL1_800M_CLK,
160 SYSTEM_PLL1_400M_CLK,
161 SYSTEM_PLL1_266M_CLK,
162 SYSTEM_PLL1_200M_CLK,
163 SYSTEM_PLL1_160M_CLK,
164 SYSTEM_PLL1_133M_CLK,
165 SYSTEM_PLL1_100M_CLK,
166 SYSTEM_PLL1_80M_CLK,
167 SYSTEM_PLL1_40M_CLK,
168 SYSTEM_PLL2_1000M_CLK,
169 SYSTEM_PLL2_500M_CLK,
170 SYSTEM_PLL2_333M_CLK,
171 SYSTEM_PLL2_250M_CLK,
172 SYSTEM_PLL2_200M_CLK,
173 SYSTEM_PLL2_166M_CLK,
174 SYSTEM_PLL2_125M_CLK,
175 SYSTEM_PLL2_100M_CLK,
176 SYSTEM_PLL2_50M_CLK,
177 SYSTEM_PLL3_CLK,
178 AUDIO_PLL1_CLK,
179 AUDIO_PLL2_CLK,
180 VIDEO_PLL_CLK,
181 OSC_32K_CLK,
182 EXT_CLK_1,
183 EXT_CLK_2,
184 EXT_CLK_3,
185 EXT_CLK_4,
186 OSC_HDMI_CLK
187};
188
189enum clk_ccgr_index {
190 CCGR_DVFS = 0,
191 CCGR_ANAMIX = 1,
192 CCGR_CPU = 2,
193 CCGR_CSU = 3,
194 CCGR_DEBUG = 4,
195 CCGR_DDR1 = 5,
196 CCGR_ECSPI1 = 7,
197 CCGR_ECSPI2 = 8,
198 CCGR_ECSPI3 = 9,
199 CCGR_ENET1 = 10,
200 CCGR_GPIO1 = 11,
201 CCGR_GPIO2 = 12,
202 CCGR_GPIO3 = 13,
203 CCGR_GPIO4 = 14,
204 CCGR_GPIO5 = 15,
205 CCGR_GPT1 = 16,
206 CCGR_GPT2 = 17,
207 CCGR_GPT3 = 18,
208 CCGR_GPT4 = 19,
209 CCGR_GPT5 = 20,
210 CCGR_GPT6 = 21,
211 CCGR_HS = 22,
212 CCGR_I2C1 = 23,
213 CCGR_I2C2 = 24,
214 CCGR_I2C3 = 25,
215 CCGR_I2C4 = 26,
216 CCGR_IOMUX = 27,
217 CCGR_IOMUX1 = 28,
218 CCGR_IOMUX2 = 29,
219 CCGR_IOMUX3 = 30,
220 CCGR_IOMUX4 = 31,
221 CCGR_SNVSMIX_IPG_CLK = 32,
222 CCGR_MU = 33,
223 CCGR_OCOTP = 34,
224 CCGR_OCRAM = 35,
225 CCGR_OCRAM_S = 36,
226 CCGR_PCIE = 37,
227 CCGR_PERFMON1 = 38,
228 CCGR_PERFMON2 = 39,
229 CCGR_PWM1 = 40,
230 CCGR_PWM2 = 41,
231 CCGR_PWM3 = 42,
232 CCGR_PWM4 = 43,
233 CCGR_QOS = 44,
234 CCGR_QOS_DISPMIX = 45,
235 CCGR_QOS_ETHENET = 46,
236 CCGR_QSPI = 47,
237 CCGR_RAWNAND = 48,
238 CCGR_RDC = 49,
239 CCGR_ROM = 50,
240 CCGR_SAI1 = 51,
241 CCGR_SAI2 = 52,
242 CCGR_SAI3 = 53,
243 CCGR_SAI4 = 54,
244 CCGR_SAI5 = 55,
245 CCGR_SAI6 = 56,
246 CCGR_SCTR = 57,
247 CCGR_SDMA1 = 58,
248 CCGR_SDMA2 = 59,
249 CCGR_SEC_DEBUG = 60,
250 CCGR_SEMA1 = 61,
251 CCGR_SEMA2 = 62,
252 CCGR_SIM_DISPLAY = 63,
253 CCGR_SIM_ENET = 64,
254 CCGR_SIM_M = 65,
255 CCGR_SIM_MAIN = 66,
256 CCGR_SIM_S = 67,
257 CCGR_SIM_WAKEUP = 68,
258 CCGR_SIM_HSIO = 69,
259 CCGR_SIM_VPU = 70,
260 CCGR_SNVS = 71,
261 CCGR_TRACE = 72,
262 CCGR_UART1 = 73,
263 CCGR_UART2 = 74,
264 CCGR_UART3 = 75,
265 CCGR_UART4 = 76,
266 CCGR_USB_MSCALE_PL301 = 77,
267 CCGR_GPU3D = 79,
268 CCGR_USDHC1 = 81,
269 CCGR_USDHC2 = 82,
270 CCGR_WDOG1 = 83,
271 CCGR_WDOG2 = 84,
272 CCGR_WDOG3 = 85,
273 CCGR_VPUG1 = 86,
274 CCGR_GPU_BUS = 87,
275 CCGR_VPUH1 = 89,
276 CCGR_VPUG2 = 90,
277 CCGR_PDM = 91,
278 CCGR_GIC = 92,
279 CCGR_DISPMIX = 93,
280 CCGR_USDHC3 = 94,
281 CCGR_SDMA3 = 95,
282 CCGR_XTAL = 96,
283 CCGR_PLL = 97,
284 CCGR_TEMP_SENSOR = 98,
285 CCGR_VPUMIX_BUS = 99,
286 CCGR_GPU2D = 102,
287 CCGR_MAX
288};
289
290enum clk_src_index {
291 CLK_SRC_CKIL_SYNC_REQ = 0,
292 CLK_SRC_ARM_PLL_EN = 1,
293 CLK_SRC_GPU_PLL_EN = 2,
294 CLK_SRC_VPU_PLL_EN = 3,
295 CLK_SRC_DRAM_PLL_EN = 4,
296 CLK_SRC_SYSTEM_PLL1_EN = 5,
297 CLK_SRC_SYSTEM_PLL2_EN = 6,
298 CLK_SRC_SYSTEM_PLL3_EN = 7,
299 CLK_SRC_AUDIO_PLL1_EN = 8,
300 CLK_SRC_AUDIO_PLL2_EN = 9,
301 CLK_SRC_VIDEO_PLL1_EN = 10,
302 CLK_SRC_RESERVED = 11,
303 CLK_SRC_ARM_PLL = 12,
304 CLK_SRC_GPU_PLL = 13,
305 CLK_SRC_VPU_PLL = 14,
306 CLK_SRC_DRAM_PLL = 15,
307 CLK_SRC_SYSTEM_PLL1_800M = 16,
308 CLK_SRC_SYSTEM_PLL1_400M = 17,
309 CLK_SRC_SYSTEM_PLL1_266M = 18,
310 CLK_SRC_SYSTEM_PLL1_200M = 19,
311 CLK_SRC_SYSTEM_PLL1_160M = 20,
312 CLK_SRC_SYSTEM_PLL1_133M = 21,
313 CLK_SRC_SYSTEM_PLL1_100M = 22,
314 CLK_SRC_SYSTEM_PLL1_80M = 23,
315 CLK_SRC_SYSTEM_PLL1_40M = 24,
316 CLK_SRC_SYSTEM_PLL2_1000M = 25,
317 CLK_SRC_SYSTEM_PLL2_500M = 26,
318 CLK_SRC_SYSTEM_PLL2_333M = 27,
319 CLK_SRC_SYSTEM_PLL2_250M = 28,
320 CLK_SRC_SYSTEM_PLL2_200M = 29,
321 CLK_SRC_SYSTEM_PLL2_166M = 30,
322 CLK_SRC_SYSTEM_PLL2_125M = 31,
323 CLK_SRC_SYSTEM_PLL2_100M = 32,
324 CLK_SRC_SYSTEM_PLL2_50M = 33,
325 CLK_SRC_SYSTEM_PLL3 = 34,
326 CLK_SRC_AUDIO_PLL1 = 35,
327 CLK_SRC_AUDIO_PLL2 = 36,
328 CLK_SRC_VIDEO_PLL1 = 37,
329};
330
331#define INTPLL_LOCK_MASK BIT(31)
332#define INTPLL_LOCK_SEL_MASK BIT(29)
333#define INTPLL_EXT_BYPASS_MASK BIT(28)
334#define INTPLL_DIV20_CLKE_MASK BIT(27)
335#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
336#define INTPLL_DIV10_CLKE_MASK BIT(25)
337#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
338#define INTPLL_DIV8_CLKE_MASK BIT(23)
339#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
340#define INTPLL_DIV6_CLKE_MASK BIT(21)
341#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
342#define INTPLL_DIV5_CLKE_MASK BIT(19)
343#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
344#define INTPLL_DIV4_CLKE_MASK BIT(17)
345#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
346#define INTPLL_DIV3_CLKE_MASK BIT(15)
347#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
348#define INTPLL_DIV2_CLKE_MASK BIT(13)
349#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
350#define INTPLL_CLKE_MASK BIT(11)
351#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
352#define INTPLL_RST_MASK BIT(9)
353#define INTPLL_RST_OVERRIDE_MASK BIT(8)
354#define INTPLL_BYPASS_MASK BIT(4)
355#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
356#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
357
358#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
359#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
360#define INTPLL_MAIN_DIV_SHIFT 12
361#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
362#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
363#define INTPLL_PRE_DIV_SHIFT 4
364#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
365#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
366#define INTPLL_POST_DIV_SHIFT 0
367
368#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
369#define INTPLL_LOCK_CON_DLY_SHIFT 4
370#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
371#define INTPLL_LOCK_CON_OUT_SHIFT 2
372#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
373#define INTPLL_LOCK_CON_IN_SHIFT 0
374
375#define INTPLL_LRD_EN_MASK BIT(21)
376#define INTPLL_FOUT_MASK BIT(20)
377#define INTPLL_AFC_SEL_MASK BIT(19)
378#define INTPLL_PBIAS_CTRL_MASK BIT(18)
379#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
380#define INTPLL_AFCINIT_SEL_MASK BIT(16)
381#define INTPLL_FSEL_MASK BIT(14)
382#define INTPLL_FEED_EN_MASK BIT(13)
383#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
384#define INTPLL_AFC_EN_MASK BIT(2)
385#define INTPLL_ICP_MASK GENMASK(1, 0)
386
387#endif