Suniel Mahesh | f1cd07b | 2020-02-03 19:20:04 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
Suniel Mahesh | f1cd07b | 2020-02-03 19:20:04 +0530 | [diff] [blame] | 6 | #include <dm.h> |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 7 | #include <env.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 9 | #include <spl_gpio.h> |
| 10 | #include <asm/io.h> |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 11 | |
| 12 | #include <asm/arch-rockchip/cru.h> |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 13 | #include <asm/arch-rockchip/gpio.h> |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 14 | #include <asm/arch-rockchip/grf_rk3399.h> |
Suniel Mahesh | f1cd07b | 2020-02-03 19:20:04 +0530 | [diff] [blame] | 15 | |
Simon Glass | 49c24a8 | 2024-09-29 19:49:47 -0600 | [diff] [blame] | 16 | #ifdef CONFIG_XPL_BUILD |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 17 | |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 18 | #define PMUGRF_BASE 0xff320000 |
Jagan Teki | 6df1826 | 2020-07-21 20:36:01 +0530 | [diff] [blame] | 19 | #define GPIO0_BASE 0xff720000 |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 20 | |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 21 | /** |
| 22 | * LED setup for roc-rk3399-pc |
| 23 | * |
| 24 | * 1. Set the low power leds (only during POR, pwr_key env is 'y') |
| 25 | * glow yellow LED, termed as low power |
| 26 | * poll for on board power key press |
| 27 | * once powe key pressed, turn off yellow |
| 28 | * 2. Turn on red LED, indicating full power mode |
| 29 | */ |
Jagan Teki | 6df1826 | 2020-07-21 20:36:01 +0530 | [diff] [blame] | 30 | void led_setup(void) |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 31 | { |
| 32 | struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 33 | struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; |
| 34 | bool press_pwr_key = false; |
| 35 | |
| 36 | if (IS_ENABLED(CONFIG_SPL_ENV_SUPPORT)) { |
| 37 | env_init(); |
| 38 | env_load(); |
| 39 | if (env_get_yesno("pwr_key") == 1) |
| 40 | press_pwr_key = true; |
| 41 | } |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 42 | |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 43 | if (press_pwr_key && !strcmp(get_reset_cause(), "POR")) { |
| 44 | spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); |
| 45 | |
| 46 | spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), |
| 47 | GPIO_PULL_NORMAL); |
| 48 | while (readl(&gpio0->ext_port) & 0x20) |
| 49 | ; |
| 50 | |
| 51 | spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); |
| 52 | } |
| 53 | |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 54 | spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 55 | } |
Jagan Teki | 5969196 | 2020-07-21 20:36:04 +0530 | [diff] [blame] | 56 | |
Suniel Mahesh | fe65e71 | 2020-02-03 19:20:05 +0530 | [diff] [blame] | 57 | #endif |