Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 99618ca8dbfd33c23bde38afc3b41dfbca30d80b / . / dts / upstream / src / arm64 / renesas / r9a07g043.dtsi
blob: 2eccab9c896202f3c552a4d98d8122e60131a9e2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>
9
10/ {
11 compatible = "renesas,r9a07g043";
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 /* This value must be overridden by boards that provide it */
19 clock-frequency = <0>;
20 };
21
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 /* This value must be overridden by boards that provide it */
26 clock-frequency = <0>;
27 };
28
29 /* External CAN clock - to be overridden by boards that provide it */
30 can_clk: can-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <0>;
34 };
35
36 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
37 extal_clk: extal-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 /* This value must be overridden by the board */
41 clock-frequency = <0>;
42 };
43
44 cluster0_opp: opp-table-0 {
45 compatible = "operating-points-v2";
46 opp-shared;
47
48 opp-125000000 {
49 opp-hz = /bits/ 64 <125000000>;
50 opp-microvolt = <1100000>;
51 clock-latency-ns = <300000>;
52 };
53 opp-250000000 {
54 opp-hz = /bits/ 64 <250000000>;
55 opp-microvolt = <1100000>;
56 clock-latency-ns = <300000>;
57 };
58 opp-500000000 {
59 opp-hz = /bits/ 64 <500000000>;
60 opp-microvolt = <1100000>;
61 clock-latency-ns = <300000>;
62 };
63 opp-1000000000 {
64 opp-hz = /bits/ 64 <1000000000>;
65 opp-microvolt = <1100000>;
66 clock-latency-ns = <300000>;
67 opp-suspend;
68 };
69 };
70
71 soc: soc {
72 compatible = "simple-bus";
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 mtu3: timer@10001200 {
78 compatible = "renesas,r9a07g043-mtu3",
79 "renesas,rz-mtu3";
80 reg = <0 0x10001200 0 0xb00>;
81 interrupts = <SOC_PERIPHERAL_IRQ(170) IRQ_TYPE_EDGE_RISING>,
82 <SOC_PERIPHERAL_IRQ(171) IRQ_TYPE_EDGE_RISING>,
83 <SOC_PERIPHERAL_IRQ(172) IRQ_TYPE_EDGE_RISING>,
84 <SOC_PERIPHERAL_IRQ(173) IRQ_TYPE_EDGE_RISING>,
85 <SOC_PERIPHERAL_IRQ(174) IRQ_TYPE_EDGE_RISING>,
86 <SOC_PERIPHERAL_IRQ(175) IRQ_TYPE_EDGE_RISING>,
87 <SOC_PERIPHERAL_IRQ(176) IRQ_TYPE_EDGE_RISING>,
88 <SOC_PERIPHERAL_IRQ(177) IRQ_TYPE_EDGE_RISING>,
89 <SOC_PERIPHERAL_IRQ(178) IRQ_TYPE_EDGE_RISING>,
90 <SOC_PERIPHERAL_IRQ(179) IRQ_TYPE_EDGE_RISING>,
91 <SOC_PERIPHERAL_IRQ(180) IRQ_TYPE_EDGE_RISING>,
92 <SOC_PERIPHERAL_IRQ(181) IRQ_TYPE_EDGE_RISING>,
93 <SOC_PERIPHERAL_IRQ(182) IRQ_TYPE_EDGE_RISING>,
94 <SOC_PERIPHERAL_IRQ(183) IRQ_TYPE_EDGE_RISING>,
95 <SOC_PERIPHERAL_IRQ(184) IRQ_TYPE_EDGE_RISING>,
96 <SOC_PERIPHERAL_IRQ(185) IRQ_TYPE_EDGE_RISING>,
97 <SOC_PERIPHERAL_IRQ(186) IRQ_TYPE_EDGE_RISING>,
98 <SOC_PERIPHERAL_IRQ(187) IRQ_TYPE_EDGE_RISING>,
99 <SOC_PERIPHERAL_IRQ(188) IRQ_TYPE_EDGE_RISING>,
100 <SOC_PERIPHERAL_IRQ(189) IRQ_TYPE_EDGE_RISING>,
101 <SOC_PERIPHERAL_IRQ(190) IRQ_TYPE_EDGE_RISING>,
102 <SOC_PERIPHERAL_IRQ(191) IRQ_TYPE_EDGE_RISING>,
103 <SOC_PERIPHERAL_IRQ(192) IRQ_TYPE_EDGE_RISING>,
104 <SOC_PERIPHERAL_IRQ(193) IRQ_TYPE_EDGE_RISING>,
105 <SOC_PERIPHERAL_IRQ(194) IRQ_TYPE_EDGE_RISING>,
106 <SOC_PERIPHERAL_IRQ(195) IRQ_TYPE_EDGE_RISING>,
107 <SOC_PERIPHERAL_IRQ(196) IRQ_TYPE_EDGE_RISING>,
108 <SOC_PERIPHERAL_IRQ(197) IRQ_TYPE_EDGE_RISING>,
109 <SOC_PERIPHERAL_IRQ(198) IRQ_TYPE_EDGE_RISING>,
110 <SOC_PERIPHERAL_IRQ(199) IRQ_TYPE_EDGE_RISING>,
111 <SOC_PERIPHERAL_IRQ(200) IRQ_TYPE_EDGE_RISING>,
112 <SOC_PERIPHERAL_IRQ(201) IRQ_TYPE_EDGE_RISING>,
113 <SOC_PERIPHERAL_IRQ(202) IRQ_TYPE_EDGE_RISING>,
114 <SOC_PERIPHERAL_IRQ(203) IRQ_TYPE_EDGE_RISING>,
115 <SOC_PERIPHERAL_IRQ(204) IRQ_TYPE_EDGE_RISING>,
116 <SOC_PERIPHERAL_IRQ(205) IRQ_TYPE_EDGE_RISING>,
117 <SOC_PERIPHERAL_IRQ(206) IRQ_TYPE_EDGE_RISING>,
118 <SOC_PERIPHERAL_IRQ(207) IRQ_TYPE_EDGE_RISING>,
119 <SOC_PERIPHERAL_IRQ(208) IRQ_TYPE_EDGE_RISING>,
120 <SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
121 <SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
122 <SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
123 <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
124 <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
125 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
126 "tciv0", "tgie0", "tgif0",
127 "tgia1", "tgib1", "tciv1", "tciu1",
128 "tgia2", "tgib2", "tciv2", "tciu2",
129 "tgia3", "tgib3", "tgic3", "tgid3",
130 "tciv3",
131 "tgia4", "tgib4", "tgic4", "tgid4",
132 "tciv4",
133 "tgiu5", "tgiv5", "tgiw5",
134 "tgia6", "tgib6", "tgic6", "tgid6",
135 "tciv6",
136 "tgia7", "tgib7", "tgic7", "tgid7",
137 "tciv7",
138 "tgia8", "tgib8", "tgic8", "tgid8",
139 "tciv8", "tciu8";
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
143 #pwm-cells = <2>;
144 status = "disabled";
145 };
146
147 ssi0: ssi@10049c00 {
148 compatible = "renesas,r9a07g043-ssi",
149 "renesas,rz-ssi";
150 reg = <0 0x10049c00 0 0x400>;
151 interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
152 <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
153 <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>;
154 interrupt-names = "int_req", "dma_rx", "dma_tx";
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
157 <&audio_clk1>, <&audio_clk2>;
158 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
160 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
161 dma-names = "tx", "rx";
162 power-domains = <&cpg>;
163 #sound-dai-cells = <0>;
164 status = "disabled";
165 };
166
167 ssi1: ssi@1004a000 {
168 compatible = "renesas,r9a07g043-ssi",
169 "renesas,rz-ssi";
170 reg = <0 0x1004a000 0 0x400>;
171 interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
172 <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
173 <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>;
174 interrupt-names = "int_req", "dma_rx", "dma_tx";
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
177 <&audio_clk1>, <&audio_clk2>;
178 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
179 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
180 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
181 dma-names = "tx", "rx";
182 power-domains = <&cpg>;
183 #sound-dai-cells = <0>;
184 status = "disabled";
185 };
186
187 ssi2: ssi@1004a400 {
188 compatible = "renesas,r9a07g043-ssi",
189 "renesas,rz-ssi";
190 reg = <0 0x1004a400 0 0x400>;
191 interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
192 <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
193 interrupt-names = "int_req", "dma_rt";
194 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
195 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
196 <&audio_clk1>, <&audio_clk2>;
197 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
198 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
199 dmas = <&dmac 0x265f>;
200 dma-names = "rt";
201 power-domains = <&cpg>;
202 #sound-dai-cells = <0>;
203 status = "disabled";
204 };
205
206 ssi3: ssi@1004a800 {
207 compatible = "renesas,r9a07g043-ssi",
208 "renesas,rz-ssi";
209 reg = <0 0x1004a800 0 0x400>;
210 interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
211 <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
212 <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>;
213 interrupt-names = "int_req", "dma_rx", "dma_tx";
214 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
215 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
216 <&audio_clk1>, <&audio_clk2>;
217 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
218 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
219 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
220 dma-names = "tx", "rx";
221 power-domains = <&cpg>;
222 #sound-dai-cells = <0>;
223 status = "disabled";
224 };
225
226 spi0: spi@1004ac00 {
227 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
228 reg = <0 0x1004ac00 0 0x400>;
229 interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>,
230 <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>,
231 <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-names = "error", "rx", "tx";
233 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
234 resets = <&cpg R9A07G043_RSPI0_RST>;
235 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
236 dma-names = "tx", "rx";
237 power-domains = <&cpg>;
238 num-cs = <1>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 status = "disabled";
242 };
243
244 spi1: spi@1004b000 {
245 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
246 reg = <0 0x1004b000 0 0x400>;
247 interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>,
248 <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>,
249 <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-names = "error", "rx", "tx";
251 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
252 resets = <&cpg R9A07G043_RSPI1_RST>;
253 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
254 dma-names = "tx", "rx";
255 power-domains = <&cpg>;
256 num-cs = <1>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 status = "disabled";
260 };
261
262 spi2: spi@1004b400 {
263 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
264 reg = <0 0x1004b400 0 0x400>;
265 interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>,
266 <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>,
267 <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-names = "error", "rx", "tx";
269 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
270 resets = <&cpg R9A07G043_RSPI2_RST>;
271 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
272 dma-names = "tx", "rx";
273 power-domains = <&cpg>;
274 num-cs = <1>;
275 #address-cells = <1>;
276 #size-cells = <0>;
277 status = "disabled";
278 };
279
280 scif0: serial@1004b800 {
281 compatible = "renesas,scif-r9a07g043",
282 "renesas,scif-r9a07g044";
283 reg = <0 0x1004b800 0 0x400>;
284 interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>,
285 <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>,
286 <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>,
287 <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>,
288 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>,
289 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "eri", "rxi", "txi",
291 "bri", "dri", "tei";
292 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
293 clock-names = "fck";
294 power-domains = <&cpg>;
295 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
296 status = "disabled";
297 };
298
299 scif1: serial@1004bc00 {
300 compatible = "renesas,scif-r9a07g043",
301 "renesas,scif-r9a07g044";
302 reg = <0 0x1004bc00 0 0x400>;
303 interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>,
304 <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>,
305 <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>,
306 <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>,
307 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>,
308 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "eri", "rxi", "txi",
310 "bri", "dri", "tei";
311 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
312 clock-names = "fck";
313 power-domains = <&cpg>;
314 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
315 status = "disabled";
316 };
317
318 scif2: serial@1004c000 {
319 compatible = "renesas,scif-r9a07g043",
320 "renesas,scif-r9a07g044";
321 reg = <0 0x1004c000 0 0x400>;
322 interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>,
323 <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>,
324 <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>,
325 <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>,
326 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>,
327 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>;
328 interrupt-names = "eri", "rxi", "txi",
329 "bri", "dri", "tei";
330 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
331 clock-names = "fck";
332 power-domains = <&cpg>;
333 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
334 status = "disabled";
335 };
336
337 scif3: serial@1004c400 {
338 compatible = "renesas,scif-r9a07g043",
339 "renesas,scif-r9a07g044";
340 reg = <0 0x1004c400 0 0x400>;
341 interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>,
342 <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>,
343 <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>,
344 <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>,
345 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>,
346 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-names = "eri", "rxi", "txi",
348 "bri", "dri", "tei";
349 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
350 clock-names = "fck";
351 power-domains = <&cpg>;
352 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
353 status = "disabled";
354 };
355
356 scif4: serial@1004c800 {
357 compatible = "renesas,scif-r9a07g043",
358 "renesas,scif-r9a07g044";
359 reg = <0 0x1004c800 0 0x400>;
360 interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>,
361 <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>,
362 <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>,
363 <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>,
364 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>,
365 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>;
366 interrupt-names = "eri", "rxi", "txi",
367 "bri", "dri", "tei";
368 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
369 clock-names = "fck";
370 power-domains = <&cpg>;
371 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
372 status = "disabled";
373 };
374
375 sci0: serial@1004d000 {
376 compatible = "renesas,r9a07g043-sci", "renesas,sci";
377 reg = <0 0x1004d000 0 0x400>;
378 interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>,
379 <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>,
380 <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>,
381 <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "eri", "rxi", "txi", "tei";
383 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
384 clock-names = "fck";
385 power-domains = <&cpg>;
386 resets = <&cpg R9A07G043_SCI0_RST>;
387 status = "disabled";
388 };
389
390 sci1: serial@1004d400 {
391 compatible = "renesas,r9a07g043-sci", "renesas,sci";
392 reg = <0 0x1004d400 0 0x400>;
393 interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>,
394 <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>,
395 <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>,
396 <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "eri", "rxi", "txi", "tei";
398 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
399 clock-names = "fck";
400 power-domains = <&cpg>;
401 resets = <&cpg R9A07G043_SCI1_RST>;
402 status = "disabled";
403 };
404
405 canfd: can@10050000 {
406 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
407 reg = <0 0x10050000 0 0x8000>;
408 interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>,
409 <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>,
410 <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>,
411 <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>,
412 <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>,
413 <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>,
414 <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>,
415 <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-names = "g_err", "g_recc",
417 "ch0_err", "ch0_rec", "ch0_trx",
418 "ch1_err", "ch1_rec", "ch1_trx";
419 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
420 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
421 <&can_clk>;
422 clock-names = "fck", "canfd", "can_clk";
423 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
424 assigned-clock-rates = <50000000>;
425 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
426 <&cpg R9A07G043_CANFD_RSTC_N>;
427 reset-names = "rstp_n", "rstc_n";
428 power-domains = <&cpg>;
429 status = "disabled";
430
431 channel0 {
432 status = "disabled";
433 };
434 channel1 {
435 status = "disabled";
436 };
437 };
438
439 i2c0: i2c@10058000 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
443 reg = <0 0x10058000 0 0x400>;
444 interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>,
445 <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>,
446 <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>,
447 <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>,
448 <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>,
449 <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>,
450 <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>,
451 <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>;
452 interrupt-names = "tei", "ri", "ti", "spi", "sti",
453 "naki", "ali", "tmoi";
454 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
455 clock-frequency = <100000>;
456 resets = <&cpg R9A07G043_I2C0_MRST>;
457 power-domains = <&cpg>;
458 status = "disabled";
459 };
460
461 i2c1: i2c@10058400 {
462 #address-cells = <1>;
463 #size-cells = <0>;
464 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
465 reg = <0 0x10058400 0 0x400>;
466 interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>,
467 <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>,
468 <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>,
469 <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>,
470 <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>,
471 <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>,
472 <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>,
473 <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "tei", "ri", "ti", "spi", "sti",
475 "naki", "ali", "tmoi";
476 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
477 clock-frequency = <100000>;
478 resets = <&cpg R9A07G043_I2C1_MRST>;
479 power-domains = <&cpg>;
480 status = "disabled";
481 };
482
483 i2c2: i2c@10058800 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
487 reg = <0 0x10058800 0 0x400>;
488 interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>,
489 <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>,
490 <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>,
491 <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>,
492 <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>,
493 <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>,
494 <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>,
495 <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-names = "tei", "ri", "ti", "spi", "sti",
497 "naki", "ali", "tmoi";
498 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
499 clock-frequency = <100000>;
500 resets = <&cpg R9A07G043_I2C2_MRST>;
501 power-domains = <&cpg>;
502 status = "disabled";
503 };
504
505 i2c3: i2c@10058c00 {
506 #address-cells = <1>;
507 #size-cells = <0>;
508 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
509 reg = <0 0x10058c00 0 0x400>;
510 interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>,
511 <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>,
512 <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>,
513 <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>,
514 <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>,
515 <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>,
516 <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>,
517 <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>;
518 interrupt-names = "tei", "ri", "ti", "spi", "sti",
519 "naki", "ali", "tmoi";
520 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
521 clock-frequency = <100000>;
522 resets = <&cpg R9A07G043_I2C3_MRST>;
523 power-domains = <&cpg>;
524 status = "disabled";
525 };
526
527 adc: adc@10059000 {
528 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
529 reg = <0 0x10059000 0 0x400>;
530 interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>;
531 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
532 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
533 clock-names = "adclk", "pclk";
534 resets = <&cpg R9A07G043_ADC_PRESETN>,
535 <&cpg R9A07G043_ADC_ADRST_N>;
536 reset-names = "presetn", "adrst-n";
537 power-domains = <&cpg>;
538 status = "disabled";
539
540 #address-cells = <1>;
541 #size-cells = <0>;
542
543 channel@0 {
544 reg = <0>;
545 };
546 channel@1 {
547 reg = <1>;
548 };
549 };
550
551 tsu: thermal@10059400 {
552 compatible = "renesas,r9a07g043-tsu",
553 "renesas,rzg2l-tsu";
554 reg = <0 0x10059400 0 0x400>;
555 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
556 resets = <&cpg R9A07G043_TSU_PRESETN>;
557 power-domains = <&cpg>;
558 #thermal-sensor-cells = <1>;
559 };
560
561 sbc: spi@10060000 {
562 compatible = "renesas,r9a07g043-rpc-if",
563 "renesas,rzg2l-rpc-if";
564 reg = <0 0x10060000 0 0x10000>,
565 <0 0x20000000 0 0x10000000>,
566 <0 0x10070000 0 0x10000>;
567 reg-names = "regs", "dirmap", "wbuf";
568 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
569 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
570 resets = <&cpg R9A07G043_SPI_RST>;
571 power-domains = <&cpg>;
572 #address-cells = <1>;
573 #size-cells = <0>;
574 status = "disabled";
575 };
576
577 cpg: clock-controller@11010000 {
578 compatible = "renesas,r9a07g043-cpg";
579 reg = <0 0x11010000 0 0x10000>;
580 clocks = <&extal_clk>;
581 clock-names = "extal";
582 #clock-cells = <2>;
583 #reset-cells = <1>;
584 #power-domain-cells = <0>;
585 };
586
587 sysc: system-controller@11020000 {
588 compatible = "renesas,r9a07g043-sysc";
589 reg = <0 0x11020000 0 0x10000>;
590 status = "disabled";
591 };
592
593 pinctrl: pinctrl@11030000 {
594 compatible = "renesas,r9a07g043-pinctrl";
595 reg = <0 0x11030000 0 0x10000>;
596 gpio-controller;
597 #gpio-cells = <2>;
598 gpio-ranges = <&pinctrl 0 0 152>;
599 #interrupt-cells = <2>;
600 interrupt-controller;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]601 interrupt-parent = <&irqc>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]602 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
603 power-domains = <&cpg>;
604 resets = <&cpg R9A07G043_GPIO_RSTN>,
605 <&cpg R9A07G043_GPIO_PORT_RESETN>,
606 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
607 };
608
609 dmac: dma-controller@11820000 {
610 compatible = "renesas,r9a07g043-dmac",
611 "renesas,rz-dmac";
612 reg = <0 0x11820000 0 0x10000>,
613 <0 0x11830000 0 0x10000>;
614 interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>,
615 <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>,
616 <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>,
617 <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>,
618 <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>,
619 <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>,
620 <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>,
621 <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>,
622 <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>,
623 <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>,
624 <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>,
625 <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>,
626 <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>,
627 <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>,
628 <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>,
629 <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>,
630 <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
631 interrupt-names = "error",
632 "ch0", "ch1", "ch2", "ch3",
633 "ch4", "ch5", "ch6", "ch7",
634 "ch8", "ch9", "ch10", "ch11",
635 "ch12", "ch13", "ch14", "ch15";
636 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
637 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
638 clock-names = "main", "register";
639 power-domains = <&cpg>;
640 resets = <&cpg R9A07G043_DMAC_ARESETN>,
641 <&cpg R9A07G043_DMAC_RST_ASYNC>;
642 reset-names = "arst", "rst_async";
643 #dma-cells = <1>;
644 dma-channels = <16>;
645 };
646
647 sdhi0: mmc@11c00000 {
648 compatible = "renesas,sdhi-r9a07g043",
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]649 "renesas,rzg2l-sdhi";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]650 reg = <0x0 0x11c00000 0 0x10000>;
651 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
652 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
654 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
655 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
656 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
657 clock-names = "core", "clkh", "cd", "aclk";
658 resets = <&cpg R9A07G043_SDHI0_IXRST>;
659 power-domains = <&cpg>;
660 status = "disabled";
661 };
662
663 sdhi1: mmc@11c10000 {
664 compatible = "renesas,sdhi-r9a07g043",
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]665 "renesas,rzg2l-sdhi";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]666 reg = <0x0 0x11c10000 0 0x10000>;
667 interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
668 <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
670 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
671 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
672 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
673 clock-names = "core", "clkh", "cd", "aclk";
674 resets = <&cpg R9A07G043_SDHI1_IXRST>;
675 power-domains = <&cpg>;
676 status = "disabled";
677 };
678
679 eth0: ethernet@11c20000 {
680 compatible = "renesas,r9a07g043-gbeth",
681 "renesas,rzg2l-gbeth";
682 reg = <0 0x11c20000 0 0x10000>;
683 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>,
684 <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>,
685 <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>;
686 interrupt-names = "mux", "fil", "arp_ns";
687 phy-mode = "rgmii";
688 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
689 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
690 <&cpg CPG_CORE R9A07G043_CLK_HP>;
691 clock-names = "axi", "chi", "refclk";
692 resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
693 power-domains = <&cpg>;
694 #address-cells = <1>;
695 #size-cells = <0>;
696 status = "disabled";
697 };
698
699 eth1: ethernet@11c30000 {
700 compatible = "renesas,r9a07g043-gbeth",
701 "renesas,rzg2l-gbeth";
702 reg = <0 0x11c30000 0 0x10000>;
703 interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>,
704 <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>,
705 <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-names = "mux", "fil", "arp_ns";
707 phy-mode = "rgmii";
708 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
709 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
710 <&cpg CPG_CORE R9A07G043_CLK_HP>;
711 clock-names = "axi", "chi", "refclk";
712 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
713 power-domains = <&cpg>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 status = "disabled";
717 };
718
719 phyrst: usbphy-ctrl@11c40000 {
720 compatible = "renesas,r9a07g043-usbphy-ctrl",
721 "renesas,rzg2l-usbphy-ctrl";
722 reg = <0 0x11c40000 0 0x10000>;
723 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
724 resets = <&cpg R9A07G043_USB_PRESETN>;
725 power-domains = <&cpg>;
726 #reset-cells = <1>;
727 status = "disabled";
728 };
729
730 ohci0: usb@11c50000 {
731 compatible = "generic-ohci";
732 reg = <0 0x11c50000 0 0x100>;
733 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
735 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
736 resets = <&phyrst 0>,
737 <&cpg R9A07G043_USB_U2H0_HRESETN>;
738 phys = <&usb2_phy0 1>;
739 phy-names = "usb";
740 power-domains = <&cpg>;
741 status = "disabled";
742 };
743
744 ohci1: usb@11c70000 {
745 compatible = "generic-ohci";
746 reg = <0 0x11c70000 0 0x100>;
747 interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
749 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
750 resets = <&phyrst 1>,
751 <&cpg R9A07G043_USB_U2H1_HRESETN>;
752 phys = <&usb2_phy1 1>;
753 phy-names = "usb";
754 power-domains = <&cpg>;
755 status = "disabled";
756 };
757
758 ehci0: usb@11c50100 {
759 compatible = "generic-ehci";
760 reg = <0 0x11c50100 0 0x100>;
761 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
763 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
764 resets = <&phyrst 0>,
765 <&cpg R9A07G043_USB_U2H0_HRESETN>;
766 phys = <&usb2_phy0 2>;
767 phy-names = "usb";
768 companion = <&ohci0>;
769 power-domains = <&cpg>;
770 status = "disabled";
771 };
772
773 ehci1: usb@11c70100 {
774 compatible = "generic-ehci";
775 reg = <0 0x11c70100 0 0x100>;
776 interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
778 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
779 resets = <&phyrst 1>,
780 <&cpg R9A07G043_USB_U2H1_HRESETN>;
781 phys = <&usb2_phy1 2>;
782 phy-names = "usb";
783 companion = <&ohci1>;
784 power-domains = <&cpg>;
785 status = "disabled";
786 };
787
788 usb2_phy0: usb-phy@11c50200 {
789 compatible = "renesas,usb2-phy-r9a07g043",
790 "renesas,rzg2l-usb2-phy";
791 reg = <0 0x11c50200 0 0x700>;
792 interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
794 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
795 resets = <&phyrst 0>;
796 #phy-cells = <1>;
797 power-domains = <&cpg>;
798 status = "disabled";
799 };
800
801 usb2_phy1: usb-phy@11c70200 {
802 compatible = "renesas,usb2-phy-r9a07g043",
803 "renesas,rzg2l-usb2-phy";
804 reg = <0 0x11c70200 0 0x700>;
805 interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
807 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
808 resets = <&phyrst 1>;
809 #phy-cells = <1>;
810 power-domains = <&cpg>;
811 status = "disabled";
812 };
813
814 hsusb: usb@11c60000 {
815 compatible = "renesas,usbhs-r9a07g043",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]816 "renesas,rzg2l-usbhs";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]817 reg = <0 0x11c60000 0 0x10000>;
818 interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>,
819 <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>,
820 <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>,
821 <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
823 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
824 resets = <&phyrst 0>,
825 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
826 renesas,buswait = <7>;
827 phys = <&usb2_phy0 3>;
828 phy-names = "usb";
829 power-domains = <&cpg>;
830 status = "disabled";
831 };
832
833 wdt0: watchdog@12800800 {
834 compatible = "renesas,r9a07g043-wdt",
835 "renesas,rzg2l-wdt";
836 reg = <0 0x12800800 0 0x400>;
837 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
838 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
839 clock-names = "pclk", "oscclk";
840 interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>,
841 <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
842 interrupt-names = "wdt", "perrout";
843 resets = <&cpg R9A07G043_WDT0_PRESETN>;
844 power-domains = <&cpg>;
845 status = "disabled";
846 };
847
848 ostm0: timer@12801000 {
849 compatible = "renesas,r9a07g043-ostm",
850 "renesas,ostm";
851 reg = <0x0 0x12801000 0x0 0x400>;
852 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>;
853 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
854 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
855 power-domains = <&cpg>;
856 status = "disabled";
857 };
858
859 ostm1: timer@12801400 {
860 compatible = "renesas,r9a07g043-ostm",
861 "renesas,ostm";
862 reg = <0x0 0x12801400 0x0 0x400>;
863 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>;
864 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
865 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
866 power-domains = <&cpg>;
867 status = "disabled";
868 };
869
870 ostm2: timer@12801800 {
871 compatible = "renesas,r9a07g043-ostm",
872 "renesas,ostm";
873 reg = <0x0 0x12801800 0x0 0x400>;
874 interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>;
875 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
876 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
877 power-domains = <&cpg>;
878 status = "disabled";
879 };
880 };
881
882 thermal-zones {
883 cpu-thermal {
884 polling-delay-passive = <250>;
885 polling-delay = <1000>;
886 thermal-sensors = <&tsu 0>;
887 sustainable-power = <717>;
888
889 cooling-maps {
890 map0 {
891 trip = <&target>;
892 cooling-device = <&cpu0 0 2>;
893 contribution = <1024>;
894 };
895 };
896
897 trips {
898 sensor_crit: sensor-crit {
899 temperature = <125000>;
900 hysteresis = <1000>;
901 type = "critical";
902 };
903
904 target: trip-point {
905 temperature = <100000>;
906 hysteresis = <1000>;
907 type = "passive";
908 };
909 };
910 };
911 };
912};