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Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for MediaTek X20 Development Board
4 *
5 * Copyright (C) 2018, Linaro Ltd.
6 *
7 */
8
9/dts-v1/;
10
11#include "mt6797.dtsi"
12
13/ {
14 model = "Mediatek X20 Development Board";
15 chassis-type = "embedded";
16 compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
17
18 aliases {
19 serial0 = &uart1;
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0 0x40000000 0 0x80000000>;
25 };
26
27 chosen {
28 stdout-path = "serial0:115200n8";
29 };
30};
31
32/* HDMI */
33&i2c1 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c1_pins_a>;
36 status = "okay";
37};
38
39/* HS - I2C2 */
40&i2c2 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&i2c2_pins_a>;
43 status = "okay";
44};
45
46/* HS - I2C3 */
47&i2c3 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&i2c3_pins_a>;
50 status = "okay";
51};
52
53/* LS - I2C0 */
54&i2c4 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&i2c4_pins_a>;
57 status = "okay";
58};
59
60/* LS - I2C1 */
61&i2c5 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&i2c5_pins_a>;
64 status = "okay";
65};
66
67/* POWER_VPROC */
68&i2c6 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&i2c6_pins_a>;
71 status = "okay";
72};
73
74/* FAN53555 */
75&i2c7 {
76 pinctrl-names = "default";
77 pinctrl-0 = <&i2c7_pins_a>;
78 status = "okay";
79};
80
81&uart1 {
82 status = "okay";
83 pinctrl-names = "default";
84 pinctrl-0 = <&uart1_pins_a>;
85};