| Jerome Brunet | 993709a | 2019-02-08 16:23:20 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 BayLibre, SAS |
| 4 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __G12A_H__ |
| 8 | #define __G12A_H__ |
| 9 | |
| 10 | #define G12A_AOBUS_BASE 0xff800000 |
| 11 | #define G12A_PERIPHS_BASE 0xff634400 |
| 12 | #define G12A_HIU_BASE 0xff63c000 |
| 13 | #define G12A_ETH_PHY_BASE 0xff64c000 |
| 14 | #define G12A_ETH_BASE 0xff3f0000 |
| 15 | |
| 16 | /* Always-On Peripherals registers */ |
| 17 | #define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) |
| 18 | |
| 19 | #define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) |
| 20 | #define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) |
| 21 | #define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) |
| 22 | #define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) |
| 23 | |
| 24 | #define G12A_AO_BOOT_DEVICE 0xF |
| 25 | #define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 |
| 26 | #define G12A_AO_MEM_SIZE_SHIFT 16 |
| 27 | #define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 |
| 28 | #define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 |
| 29 | #define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF |
| 30 | |
| 31 | /* Peripherals registers */ |
| 32 | #define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) |
| 33 | |
| 34 | #define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) |
| 35 | #define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) |
| 36 | |
| 37 | #define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) |
| 38 | #define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) |
| 39 | #define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) |
| 40 | #define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) |
| 41 | #define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) |
| 42 | #define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) |
| 43 | #define G12A_ETH_REG_0_CLK_EN BIT(12) |
| 44 | |
| 45 | #define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) |
| 46 | #define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) |
| 47 | #define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) |
| 48 | #define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) |
| 49 | #define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) |
| 50 | #define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) |
| 51 | #define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) |
| 52 | #define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) |
| 53 | #define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) |
| 54 | #define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) |
| 55 | #define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) |
| 56 | #define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) |
| 57 | |
| 58 | /* HIU registers */ |
| 59 | #define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) |
| 60 | |
| 61 | #define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) |
| 62 | |
| 63 | /* Ethernet memory power domain */ |
| 64 | #define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) |
| 65 | |
| 66 | #endif /* __G12A_H__ */ |