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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liu07886942013-11-22 17:39:11 +08002/*
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
Biwen Li07b3dcf2020-05-01 20:04:19 +08004 * Copyright 2020 NXP
Shengzhou Liu07886942013-11-22 17:39:11 +08005 */
6
7/*
Shengzhou Liu031228a2014-02-21 13:16:19 +08008 * T2080/T2081 QDS board configuration file
Shengzhou Liu07886942013-11-22 17:39:11 +08009 */
10
Shengzhou Liu031228a2014-02-21 13:16:19 +080011#ifndef __T208xQDS_H
12#define __T208xQDS_H
Shengzhou Liu07886942013-11-22 17:39:11 +080013
Simon Glassfb64e362020-05-10 11:40:09 -060014#include <linux/stringify.h>
15
Shengzhou Liu07886942013-11-22 17:39:11 +080016#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
York Sune20c6852016-11-21 12:54:19 -080017#if defined(CONFIG_ARCH_T2080)
Shengzhou Liu07886942013-11-22 17:39:11 +080018#define CONFIG_FSL_SATA_V2
19#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
20#define CONFIG_SRIO1 /* SRIO port 1 */
21#define CONFIG_SRIO2 /* SRIO port 2 */
York Sune20c6852016-11-21 12:54:19 -080022#elif defined(CONFIG_ARCH_T2081)
Shengzhou Liu031228a2014-02-21 13:16:19 +080023#endif
Shengzhou Liu07886942013-11-22 17:39:11 +080024
25/* High Level Configuration Options */
Shengzhou Liu07886942013-11-22 17:39:11 +080026#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liu07886942013-11-22 17:39:11 +080027#define CONFIG_ENABLE_36BIT_PHYS
28
Shengzhou Liu07886942013-11-22 17:39:11 +080029#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sunfe845072016-12-28 08:43:45 -080030#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Shengzhou Liu07886942013-11-22 17:39:11 +080031#define CONFIG_ENV_OVERWRITE
32
33#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090034#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080035
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080036#define CONFIG_SPL_FLUSH_IMAGE
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080037#define CONFIG_SPL_PAD_TO 0x40000
38#define CONFIG_SPL_MAX_SIZE 0x28000
39#define RESET_VECTOR_OFFSET 0x27FFC
40#define BOOT_PAGE_OFFSET 0x27000
41#ifdef CONFIG_SPL_BUILD
42#define CONFIG_SPL_SKIP_RELOCATE
43#define CONFIG_SPL_COMMON_INIT_DDR
44#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080045#endif
46
Miquel Raynald0935362019-10-03 19:50:03 +020047#ifdef CONFIG_MTD_RAW_NAND
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080048#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
York Sune20c6852016-11-21 12:54:19 -080052#if defined(CONFIG_ARCH_T2080)
Zhao Qiang55107dc2016-09-08 12:55:32 +080053#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
York Sune20c6852016-11-21 12:54:19 -080054#elif defined(CONFIG_ARCH_T2081)
Zhao Qiang55107dc2016-09-08 12:55:32 +080055#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
56#endif
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080057#endif
58
59#ifdef CONFIG_SPIFLASH
60#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080061#define CONFIG_SPL_SPI_FLASH_MINIMAL
62#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
63#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
64#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
65#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080066#ifndef CONFIG_SPL_BUILD
67#define CONFIG_SYS_MPC85XX_NO_RESETVEC
68#endif
York Sune20c6852016-11-21 12:54:19 -080069#if defined(CONFIG_ARCH_T2080)
Zhao Qiang55107dc2016-09-08 12:55:32 +080070#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
York Sune20c6852016-11-21 12:54:19 -080071#elif defined(CONFIG_ARCH_T2081)
Zhao Qiang55107dc2016-09-08 12:55:32 +080072#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
73#endif
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080074#endif
75
76#ifdef CONFIG_SDCARD
77#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080078#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
79#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
80#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
81#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080082#ifndef CONFIG_SPL_BUILD
83#define CONFIG_SYS_MPC85XX_NO_RESETVEC
84#endif
York Sune20c6852016-11-21 12:54:19 -080085#if defined(CONFIG_ARCH_T2080)
Zhao Qiang55107dc2016-09-08 12:55:32 +080086#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
York Sune20c6852016-11-21 12:54:19 -080087#elif defined(CONFIG_ARCH_T2081)
Zhao Qiang55107dc2016-09-08 12:55:32 +080088#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
89#endif
Shengzhou Liu07886942013-11-22 17:39:11 +080090#endif
91
Shengzhou Liud11b3cb2014-04-18 16:43:39 +080092#endif /* CONFIG_RAMBOOT_PBL */
93
Shengzhou Liu07886942013-11-22 17:39:11 +080094#define CONFIG_SRIO_PCIE_BOOT_MASTER
95#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
96/* Set 1M boot space */
97#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
98#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
99 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
100#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shengzhou Liu07886942013-11-22 17:39:11 +0800101#endif
102
Shengzhou Liu07886942013-11-22 17:39:11 +0800103#ifndef CONFIG_RESET_VECTOR_ADDRESS
104#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
105#endif
106
107/*
108 * These can be toggled for performance analysis, otherwise use default.
109 */
110#define CONFIG_SYS_CACHE_STASHING
111#define CONFIG_BTB /* toggle branch predition */
112#define CONFIG_DDR_ECC
113#ifdef CONFIG_DDR_ECC
114#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
115#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
116#endif
117
Shengzhou Liu07886942013-11-22 17:39:11 +0800118#if defined(CONFIG_SPIFLASH)
Shengzhou Liu07886942013-11-22 17:39:11 +0800119#elif defined(CONFIG_SDCARD)
Shengzhou Liu07886942013-11-22 17:39:11 +0800120#define CONFIG_SYS_MMC_ENV_DEV 0
Shengzhou Liu07886942013-11-22 17:39:11 +0800121#endif
122
123#ifndef __ASSEMBLY__
124unsigned long get_board_sys_clk(void);
125unsigned long get_board_ddr_clk(void);
126#endif
127
128#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
129#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
130
131/*
132 * Config the L3 Cache as L3 SRAM
133 */
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800134#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
135#define CONFIG_SYS_L3_SIZE (512 << 10)
136#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
Tom Rini5cd7ece2019-11-18 20:02:10 -0500137#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800138#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
139#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
140#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
Shengzhou Liu07886942013-11-22 17:39:11 +0800141
142#define CONFIG_SYS_DCSRBAR 0xf0000000
143#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
144
145/* EEPROM */
146#define CONFIG_ID_EEPROM
147#define CONFIG_SYS_I2C_EEPROM_NXID
148#define CONFIG_SYS_EEPROM_BUS_NUM 0
149#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151
152/*
153 * DDR Setup
154 */
155#define CONFIG_VERY_BIG_RAM
156#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
157#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shengzhou Liueca52382014-05-20 12:08:20 +0800158#define CONFIG_DIMM_SLOTS_PER_CTLR 2
159#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Shengzhou Liu07886942013-11-22 17:39:11 +0800160#define CONFIG_DDR_SPD
Shengzhou Liu07886942013-11-22 17:39:11 +0800161#define CONFIG_SYS_SPD_BUS_NUM 0
162#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
163#define SPD_EEPROM_ADDRESS1 0x51
164#define SPD_EEPROM_ADDRESS2 0x52
165#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
166#define CTRL_INTLV_PREFERED cacheline
167
168/*
169 * IFC Definitions
170 */
171#define CONFIG_SYS_FLASH_BASE 0xe0000000
172#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
173#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
174#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
175 + 0x8000000) | \
176 CSPR_PORT_SIZE_16 | \
177 CSPR_MSEL_NOR | \
178 CSPR_V)
179#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
180#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
181 CSPR_PORT_SIZE_16 | \
182 CSPR_MSEL_NOR | \
183 CSPR_V)
184#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
185/* NOR Flash Timing Params */
186#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
187
188#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
189 FTIM0_NOR_TEADC(0x5) | \
190 FTIM0_NOR_TEAHC(0x5))
191#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
192 FTIM1_NOR_TRAD_NOR(0x1A) |\
193 FTIM1_NOR_TSEQRAD_NOR(0x13))
194#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
195 FTIM2_NOR_TCH(0x4) | \
196 FTIM2_NOR_TWPH(0x0E) | \
197 FTIM2_NOR_TWP(0x1c))
198#define CONFIG_SYS_NOR_FTIM3 0x0
199
200#define CONFIG_SYS_FLASH_QUIET_TEST
201#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
202
203#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
205#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
206#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
207
208#define CONFIG_SYS_FLASH_EMPTY_INFO
209#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
210 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
211
212#define CONFIG_FSL_QIXIS /* use common QIXIS code */
213#define QIXIS_BASE 0xffdf0000
214#define QIXIS_LBMAP_SWITCH 6
215#define QIXIS_LBMAP_MASK 0x0f
216#define QIXIS_LBMAP_SHIFT 0
217#define QIXIS_LBMAP_DFLTBANK 0x00
218#define QIXIS_LBMAP_ALTBANK 0x04
York Sun23b3df92016-04-07 09:52:11 -0700219#define QIXIS_LBMAP_NAND 0x09
220#define QIXIS_LBMAP_SD 0x00
221#define QIXIS_RCW_SRC_NAND 0x104
222#define QIXIS_RCW_SRC_SD 0x040
Shengzhou Liu07886942013-11-22 17:39:11 +0800223#define QIXIS_RST_CTL_RESET 0x83
224#define QIXIS_RST_FORCE_MEM 0x1
225#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
226#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
227#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
228#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
229
230#define CONFIG_SYS_CSPR3_EXT (0xf)
231#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
232 | CSPR_PORT_SIZE_8 \
233 | CSPR_MSEL_GPCM \
234 | CSPR_V)
Rajesh Bhagat28663d82018-11-05 18:01:19 +0000235#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
Shengzhou Liu07886942013-11-22 17:39:11 +0800236#define CONFIG_SYS_CSOR3 0x0
237/* QIXIS Timing parameters for IFC CS3 */
238#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
239 FTIM0_GPCM_TEADC(0x0e) | \
240 FTIM0_GPCM_TEAHC(0x0e))
241#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
242 FTIM1_GPCM_TRAD(0x3f))
243#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shengzhou Liubdfeaf62014-03-06 15:07:39 +0800244 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liu07886942013-11-22 17:39:11 +0800245 FTIM2_GPCM_TWP(0x1f))
246#define CONFIG_SYS_CS3_FTIM3 0x0
247
248/* NAND Flash on IFC */
249#define CONFIG_NAND_FSL_IFC
250#define CONFIG_SYS_NAND_BASE 0xff800000
251#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
252
253#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
254#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
255 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
256 | CSPR_MSEL_NAND /* MSEL = NAND */ \
257 | CSPR_V)
258#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
259
260#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
261 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
262 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
263 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
264 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
265 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
266 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
267
268#define CONFIG_SYS_NAND_ONFI_DETECTION
269
270/* ONFI NAND Flash mode0 Timing Params */
271#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
272 FTIM0_NAND_TWP(0x18) | \
273 FTIM0_NAND_TWCHT(0x07) | \
274 FTIM0_NAND_TWH(0x0a))
275#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
276 FTIM1_NAND_TWBE(0x39) | \
277 FTIM1_NAND_TRR(0x0e) | \
278 FTIM1_NAND_TRP(0x18))
279#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
280 FTIM2_NAND_TREH(0x0a) | \
281 FTIM2_NAND_TWHRE(0x1e))
282#define CONFIG_SYS_NAND_FTIM3 0x0
283
284#define CONFIG_SYS_NAND_DDR_LAW 11
285#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
286#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu07886942013-11-22 17:39:11 +0800287#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
288
Miquel Raynald0935362019-10-03 19:50:03 +0200289#if defined(CONFIG_MTD_RAW_NAND)
Shengzhou Liu07886942013-11-22 17:39:11 +0800290#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
291#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
292#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
293#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
294#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
295#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
296#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
297#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shengzhou Liub2708d62014-03-13 10:19:00 +0800298#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
299#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
300#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
301#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
302#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
303#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
304#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
305#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
306#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
307#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
Shengzhou Liu07886942013-11-22 17:39:11 +0800308#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
309#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
310#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
311#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
312#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
313#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
314#else
315#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
316#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
317#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
318#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
319#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
320#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
321#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
322#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liub2708d62014-03-13 10:19:00 +0800323#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
324#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
325#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
326#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
327#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
328#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
329#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
330#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
Shengzhou Liu07886942013-11-22 17:39:11 +0800331#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
332#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
333#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
334#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
335#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
336#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
337#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
338#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
339#endif
Shengzhou Liu07886942013-11-22 17:39:11 +0800340
341#if defined(CONFIG_RAMBOOT_PBL)
342#define CONFIG_SYS_RAMBOOT
343#endif
344
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800345#ifdef CONFIG_SPL_BUILD
346#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
347#else
348#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
349#endif
350
Shengzhou Liu07886942013-11-22 17:39:11 +0800351#define CONFIG_HWCONFIG
352
353/* define to use L1 as initial stack */
354#define CONFIG_L1_INIT_RAM
355#define CONFIG_SYS_INIT_RAM_LOCK
356#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
357#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunee7b4832015-08-17 13:31:51 -0700358#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu07886942013-11-22 17:39:11 +0800359/* The assembler doesn't like typecast */
360#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
361 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
362 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
363#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
364#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
365 GENERATED_GBL_DATA_SIZE)
366#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530367#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu07886942013-11-22 17:39:11 +0800368#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
369
370/*
371 * Serial Port
372 */
Shengzhou Liu07886942013-11-22 17:39:11 +0800373#define CONFIG_SYS_NS16550_SERIAL
374#define CONFIG_SYS_NS16550_REG_SIZE 1
375#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
376#define CONFIG_SYS_BAUDRATE_TABLE \
377 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
378#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
379#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
380#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
381#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
382
Shengzhou Liu07886942013-11-22 17:39:11 +0800383/*
384 * I2C
385 */
Biwen Li07b3dcf2020-05-01 20:04:19 +0800386#ifndef CONFIG_DM_I2C
Shengzhou Liu07886942013-11-22 17:39:11 +0800387#define CONFIG_SYS_I2C
Shengzhou Liu07886942013-11-22 17:39:11 +0800388#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
389#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
390#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
391#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
392#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
393#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
394#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
395#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
396#define CONFIG_SYS_FSL_I2C_SPEED 100000
397#define CONFIG_SYS_FSL_I2C2_SPEED 100000
398#define CONFIG_SYS_FSL_I2C3_SPEED 100000
399#define CONFIG_SYS_FSL_I2C4_SPEED 100000
Biwen Li07b3dcf2020-05-01 20:04:19 +0800400#endif
401
402#define CONFIG_SYS_I2C_FSL
403
Shengzhou Liu07886942013-11-22 17:39:11 +0800404#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
405#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
406#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
407#define I2C_MUX_CH_DEFAULT 0x8
408
Ying Zhang8876a512014-10-31 18:06:18 +0800409#define I2C_MUX_CH_VOL_MONITOR 0xa
410
411/* Voltage monitor on channel 2*/
412#define I2C_VOL_MONITOR_ADDR 0x40
413#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
414#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
415#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
416
417#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
418#ifndef CONFIG_SPL_BUILD
419#define CONFIG_VID
420#endif
421#define CONFIG_VOL_MONITOR_IR36021_SET
422#define CONFIG_VOL_MONITOR_IR36021_READ
423/* The lowest and highest voltage allowed for T208xQDS */
424#define VDD_MV_MIN 819
425#define VDD_MV_MAX 1212
Shengzhou Liu07886942013-11-22 17:39:11 +0800426
427/*
428 * RapidIO
429 */
430#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
431#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
432#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
433#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
434#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
435#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
436/*
437 * for slave u-boot IMAGE instored in master memory space,
438 * PHYS must be aligned based on the SIZE
439 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800440#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
441#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
442#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
443#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800444/*
445 * for slave UCODE and ENV instored in master memory space,
446 * PHYS must be aligned based on the SIZE
447 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800448#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800449#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
450#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
451
452/* slave core release by master*/
453#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
454#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
455
456/*
457 * SRIO_PCIE_BOOT - SLAVE
458 */
459#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
460#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
461#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
462 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
463#endif
464
465/*
466 * eSPI - Enhanced SPI
467 */
Shengzhou Liu07886942013-11-22 17:39:11 +0800468
469/*
470 * General PCI
471 * Memory space is mapped 1-1, but I/O space must start from 0.
472 */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400473#define CONFIG_PCIE1 /* PCIE controller 1 */
474#define CONFIG_PCIE2 /* PCIE controller 2 */
475#define CONFIG_PCIE3 /* PCIE controller 3 */
476#define CONFIG_PCIE4 /* PCIE controller 4 */
Shengzhou Liu07886942013-11-22 17:39:11 +0800477#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
478/* controller 1, direct to uli, tgtid 3, Base address 20000 */
479#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Shengzhou Liu07886942013-11-22 17:39:11 +0800480#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800481#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Shengzhou Liu07886942013-11-22 17:39:11 +0800482#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800483
484/* controller 2, Slot 2, tgtid 2, Base address 201000 */
485#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Shengzhou Liu07886942013-11-22 17:39:11 +0800486#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800487#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Shengzhou Liu07886942013-11-22 17:39:11 +0800488#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800489
490/* controller 3, Slot 1, tgtid 1, Base address 202000 */
491#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Shengzhou Liu07886942013-11-22 17:39:11 +0800492#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800493#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Shengzhou Liu07886942013-11-22 17:39:11 +0800494#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800495
496/* controller 4, Base address 203000 */
497#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
Shengzhou Liu07886942013-11-22 17:39:11 +0800498#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800499#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
Shengzhou Liu07886942013-11-22 17:39:11 +0800500
501#ifdef CONFIG_PCI
Hou Zhiqiang68ec39b2019-06-20 11:20:47 +0800502#if !defined(CONFIG_DM_PCI)
503#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
504#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
505#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
506#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
507#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
508#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
509#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
510#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
511#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
512#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
513#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
514#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
515#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
516#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
517#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
518#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
519#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
Shengzhou Liu07886942013-11-22 17:39:11 +0800520#define CONFIG_PCI_INDIRECT_BRIDGE
Hou Zhiqiang68ec39b2019-06-20 11:20:47 +0800521#endif
Shengzhou Liu07886942013-11-22 17:39:11 +0800522#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Shengzhou Liu07886942013-11-22 17:39:11 +0800523#endif
524
525/* Qman/Bman */
526#ifndef CONFIG_NOBQFMAN
Shengzhou Liu07886942013-11-22 17:39:11 +0800527#define CONFIG_SYS_BMAN_NUM_PORTALS 18
528#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
529#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
530#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500531#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
532#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
533#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
534#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
535#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
536 CONFIG_SYS_BMAN_CENA_SIZE)
537#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
538#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu07886942013-11-22 17:39:11 +0800539#define CONFIG_SYS_QMAN_NUM_PORTALS 18
540#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
541#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
542#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500543#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
544#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
545#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
546#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
547#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
548 CONFIG_SYS_QMAN_CENA_SIZE)
549#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
550#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu07886942013-11-22 17:39:11 +0800551
552#define CONFIG_SYS_DPAA_FMAN
553#define CONFIG_SYS_DPAA_PME
554#define CONFIG_SYS_PMAN
555#define CONFIG_SYS_DPAA_DCE
556#define CONFIG_SYS_DPAA_RMAN /* RMan */
557#define CONFIG_SYS_INTERLAKEN
558
559/* Default address of microcode for the Linux Fman driver */
560#if defined(CONFIG_SPIFLASH)
561/*
562 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
563 * env, so we got 0x110000.
564 */
Zhao Qiang83a90842014-03-21 16:21:44 +0800565#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liu07886942013-11-22 17:39:11 +0800566#elif defined(CONFIG_SDCARD)
567/*
568 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800569 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
570 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liu07886942013-11-22 17:39:11 +0800571 */
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800572#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Miquel Raynald0935362019-10-03 19:50:03 +0200573#elif defined(CONFIG_MTD_RAW_NAND)
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800574#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu07886942013-11-22 17:39:11 +0800575#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
576/*
577 * Slave has no ucode locally, it can fetch this from remote. When implementing
578 * in two corenet boards, slave's ucode could be stored in master's memory
579 * space, the address can be mapped from slave TLB->slave LAW->
580 * slave SRIO or PCIE outbound window->master inbound window->
581 * master LAW->the ucode address in master's memory space.
582 */
Zhao Qiang83a90842014-03-21 16:21:44 +0800583#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liu07886942013-11-22 17:39:11 +0800584#else
Zhao Qiang83a90842014-03-21 16:21:44 +0800585#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liu07886942013-11-22 17:39:11 +0800586#endif
587#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
588#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
589#endif /* CONFIG_NOBQFMAN */
590
591#ifdef CONFIG_SYS_DPAA_FMAN
Shengzhou Liu07886942013-11-22 17:39:11 +0800592#define RGMII_PHY1_ADDR 0x1
593#define RGMII_PHY2_ADDR 0x2
594#define FM1_10GEC1_PHY_ADDR 0x3
595#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
596#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
597#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
598#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
599#endif
600
601#ifdef CONFIG_FMAN_ENET
Shengzhou Liu07886942013-11-22 17:39:11 +0800602#define CONFIG_ETHPRIME "FM1@DTSEC3"
Shengzhou Liu07886942013-11-22 17:39:11 +0800603#endif
604
605/*
606 * SATA
607 */
608#ifdef CONFIG_FSL_SATA_V2
Shengzhou Liu07886942013-11-22 17:39:11 +0800609#define CONFIG_SYS_SATA_MAX_DEVICE 2
610#define CONFIG_SATA1
611#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
612#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
613#define CONFIG_SATA2
614#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
615#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
616#define CONFIG_LBA48
Shengzhou Liu07886942013-11-22 17:39:11 +0800617#endif
618
619/*
620 * USB
621 */
Tom Riniceed5d22017-05-12 22:33:27 -0400622#ifdef CONFIG_USB_EHCI_HCD
Shengzhou Liu07886942013-11-22 17:39:11 +0800623#define CONFIG_USB_EHCI_FSL
624#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liu07886942013-11-22 17:39:11 +0800625#define CONFIG_HAS_FSL_DR_USB
626#endif
627
628/*
629 * SDHC
630 */
631#ifdef CONFIG_MMC
Shengzhou Liu07886942013-11-22 17:39:11 +0800632#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
633#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
634#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Yangbo Lu90a6cd32015-04-22 13:57:21 +0800635#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Shengzhou Liu07886942013-11-22 17:39:11 +0800636#endif
637
Shengzhou Liuff16bd82014-04-02 14:28:34 +0800638/*
639 * Dynamic MTD Partition support with mtdparts
640 */
Shengzhou Liuff16bd82014-04-02 14:28:34 +0800641
Shengzhou Liu07886942013-11-22 17:39:11 +0800642/*
643 * Environment
644 */
645#define CONFIG_LOADS_ECHO /* echo on for serial download */
646#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
647
648/*
Shengzhou Liu07886942013-11-22 17:39:11 +0800649 * Miscellaneous configurable options
650 */
Shengzhou Liu07886942013-11-22 17:39:11 +0800651#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu07886942013-11-22 17:39:11 +0800652
653/*
654 * For booting Linux, the board info and command line data
655 * have to be in the first 64 MB of memory, since this is
656 * the maximum mapped by the Linux kernel during initialization.
657 */
658#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
659#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
660
661#ifdef CONFIG_CMD_KGDB
662#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
663#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
664#endif
665
666/*
667 * Environment Configuration
668 */
669#define CONFIG_ROOTPATH "/opt/nfsroot"
670#define CONFIG_BOOTFILE "uImage"
671#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
672
673/* default location for tftp and bootm */
674#define CONFIG_LOADADDR 1000000
Shengzhou Liu07886942013-11-22 17:39:11 +0800675#define __USB_PHY_TYPE utmi
676
677#define CONFIG_EXTRA_ENV_SETTINGS \
678 "hwconfig=fsl_ddr:" \
679 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
680 "bank_intlv=auto;" \
681 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
682 "netdev=eth0\0" \
683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
684 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
685 "tftpflash=tftpboot $loadaddr $uboot && " \
686 "protect off $ubootaddr +$filesize && " \
687 "erase $ubootaddr +$filesize && " \
688 "cp.b $loadaddr $ubootaddr $filesize && " \
689 "protect on $ubootaddr +$filesize && " \
690 "cmp.b $loadaddr $ubootaddr $filesize\0" \
691 "consoledev=ttyS0\0" \
692 "ramdiskaddr=2000000\0" \
693 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500694 "fdtaddr=1e00000\0" \
Shengzhou Liu07886942013-11-22 17:39:11 +0800695 "fdtfile=t2080qds/t2080qds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500696 "bdev=sda3\0"
Shengzhou Liu07886942013-11-22 17:39:11 +0800697
698/*
699 * For emulation this causes u-boot to jump to the start of the
700 * proof point app code automatically
701 */
702#define CONFIG_PROOF_POINTS \
703 "setenv bootargs root=/dev/$bdev rw " \
704 "console=$consoledev,$baudrate $othbootargs;" \
705 "cpu 1 release 0x29000000 - - -;" \
706 "cpu 2 release 0x29000000 - - -;" \
707 "cpu 3 release 0x29000000 - - -;" \
708 "cpu 4 release 0x29000000 - - -;" \
709 "cpu 5 release 0x29000000 - - -;" \
710 "cpu 6 release 0x29000000 - - -;" \
711 "cpu 7 release 0x29000000 - - -;" \
712 "go 0x29000000"
713
714#define CONFIG_HVBOOT \
715 "setenv bootargs config-addr=0x60000000; " \
716 "bootm 0x01000000 - 0x00f00000"
717
718#define CONFIG_ALU \
719 "setenv bootargs root=/dev/$bdev rw " \
720 "console=$consoledev,$baudrate $othbootargs;" \
721 "cpu 1 release 0x01000000 - - -;" \
722 "cpu 2 release 0x01000000 - - -;" \
723 "cpu 3 release 0x01000000 - - -;" \
724 "cpu 4 release 0x01000000 - - -;" \
725 "cpu 5 release 0x01000000 - - -;" \
726 "cpu 6 release 0x01000000 - - -;" \
727 "cpu 7 release 0x01000000 - - -;" \
728 "go 0x01000000"
729
730#define CONFIG_LINUX \
731 "setenv bootargs root=/dev/ram rw " \
732 "console=$consoledev,$baudrate $othbootargs;" \
733 "setenv ramdiskaddr 0x02000000;" \
734 "setenv fdtaddr 0x00c00000;" \
735 "setenv loadaddr 0x1000000;" \
736 "bootm $loadaddr $ramdiskaddr $fdtaddr"
737
738#define CONFIG_HDBOOT \
739 "setenv bootargs root=/dev/$bdev rw " \
740 "console=$consoledev,$baudrate $othbootargs;" \
741 "tftp $loadaddr $bootfile;" \
742 "tftp $fdtaddr $fdtfile;" \
743 "bootm $loadaddr - $fdtaddr"
744
745#define CONFIG_NFSBOOTCOMMAND \
746 "setenv bootargs root=/dev/nfs rw " \
747 "nfsroot=$serverip:$rootpath " \
748 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $loadaddr $bootfile;" \
751 "tftp $fdtaddr $fdtfile;" \
752 "bootm $loadaddr - $fdtaddr"
753
754#define CONFIG_RAMBOOTCOMMAND \
755 "setenv bootargs root=/dev/ram rw " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "tftp $ramdiskaddr $ramdiskfile;" \
758 "tftp $loadaddr $bootfile;" \
759 "tftp $fdtaddr $fdtfile;" \
760 "bootm $loadaddr $ramdiskaddr $fdtaddr"
761
762#define CONFIG_BOOTCOMMAND CONFIG_LINUX
763
Shengzhou Liu07886942013-11-22 17:39:11 +0800764#include <asm/fsl_secure_boot.h>
Aneesh Bansal962021a2016-01-22 16:37:22 +0530765
Shengzhou Liu031228a2014-02-21 13:16:19 +0800766#endif /* __T208xQDS_H */