Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015-2016 Marvell International Ltd. |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <fdtdec.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/cpu.h> |
| 11 | #include <asm/arch/soc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 12 | #include <linux/delay.h> |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 13 | |
Marek BehĂșn | 19ce44c | 2018-08-17 12:58:51 +0200 | [diff] [blame] | 14 | #include "comphy_core.h" |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 15 | #include "comphy_hpipe.h" |
| 16 | #include "sata.h" |
| 17 | #include "utmi_phy.h" |
| 18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; |
| 20 | |
| 21 | #define SD_ADDR(base, lane) (base + 0x1000 * lane) |
| 22 | #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) |
| 23 | #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) |
| 24 | |
| 25 | struct utmi_phy_data { |
| 26 | void __iomem *utmi_base_addr; |
| 27 | void __iomem *usb_cfg_addr; |
| 28 | void __iomem *utmi_cfg_addr; |
| 29 | u32 utmi_phy_port; |
| 30 | }; |
| 31 | |
| 32 | /* |
| 33 | * For CP-110 we have 2 Selector registers "PHY Selectors", |
| 34 | * and "PIPE Selectors". |
| 35 | * PIPE selector include USB and PCIe options. |
| 36 | * PHY selector include the Ethernet and SATA options, every Ethernet |
| 37 | * option has different options, for example: serdes lane2 had option |
Stefan Roese | b8b7c67 | 2017-04-24 18:45:29 +0300 | [diff] [blame] | 38 | * Eth_port_0 that include (SGMII0, RXAUI0, SFI) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 39 | */ |
| 40 | struct comphy_mux_data cp110_comphy_phy_mux_data[] = { |
Stefan Roese | b15d61d | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 41 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ |
| 42 | {PHY_TYPE_SATA1, 0x4} } }, |
| 43 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ |
| 44 | {PHY_TYPE_SATA0, 0x4} } }, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 45 | {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ |
Stefan Roese | b15d61d | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 46 | {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, |
| 47 | {PHY_TYPE_SATA0, 0x4} } }, |
| 48 | {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ |
| 49 | {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, |
Stefan Roese | b8b7c67 | 2017-04-24 18:45:29 +0300 | [diff] [blame] | 50 | {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ |
Stefan Roese | b15d61d | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 51 | {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, |
Stefan Roese | b8b7c67 | 2017-04-24 18:45:29 +0300 | [diff] [blame] | 52 | {PHY_TYPE_SGMII1, 0x1} } }, |
Stefan Roese | b15d61d | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 53 | {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ |
| 54 | {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 55 | }; |
| 56 | |
| 57 | struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { |
| 58 | {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ |
| 59 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ |
| 60 | {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, |
| 61 | {PHY_TYPE_PEX0, 0x4} } }, |
| 62 | {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ |
| 63 | {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, |
| 64 | {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ |
| 65 | {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, |
| 66 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ |
| 67 | {PHY_TYPE_USB3_HOST1, 0x1}, |
| 68 | {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, |
| 69 | {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ |
| 70 | }; |
| 71 | |
| 72 | static u32 polling_with_timeout(void __iomem *addr, u32 val, |
| 73 | u32 mask, unsigned long usec_timout) |
| 74 | { |
| 75 | u32 data; |
| 76 | |
| 77 | do { |
| 78 | udelay(1); |
| 79 | data = readl(addr) & mask; |
| 80 | } while (data != val && --usec_timout > 0); |
| 81 | |
| 82 | if (usec_timout == 0) |
| 83 | return data; |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
Stefan Roese | 2313efe | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 88 | static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, |
| 89 | bool is_end_point, void __iomem *hpipe_base, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 90 | void __iomem *comphy_base) |
| 91 | { |
| 92 | u32 mask, data, ret = 1; |
| 93 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 94 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 95 | void __iomem *addr; |
| 96 | u32 pcie_clk = 0; /* set input by default */ |
| 97 | |
| 98 | debug_enter(); |
| 99 | |
| 100 | /* |
| 101 | * ToDo: |
| 102 | * Add SAR (Sample-At-Reset) configuration for the PCIe clock |
| 103 | * direction. SAR code is currently not ported from Marvell |
| 104 | * U-Boot to mainline version. |
| 105 | * |
| 106 | * SerDes Lane 4/5 got the PCIe ref-clock #1, |
| 107 | * and SerDes Lane 0 got PCIe ref-clock #0 |
| 108 | */ |
| 109 | debug("PCIe clock = %x\n", pcie_clk); |
Stefan Roese | 2313efe | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 110 | debug("PCIe RC = %d\n", !is_end_point); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 111 | debug("PCIe width = %d\n", pcie_width); |
| 112 | |
| 113 | /* enable PCIe by4 and by2 */ |
| 114 | if (lane == 0) { |
| 115 | if (pcie_width == 4) { |
| 116 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 117 | 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, |
| 118 | COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); |
| 119 | } else if (pcie_width == 2) { |
| 120 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 121 | 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, |
| 122 | COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | /* |
| 127 | * If PCIe clock is output and clock source from SerDes lane 5, |
| 128 | * we need to configure the clock-source MUX. |
| 129 | * By default, the clock source is from lane 4 |
| 130 | */ |
| 131 | if (pcie_clk && clk_src && (lane == 5)) { |
| 132 | reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, |
| 133 | 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, |
| 134 | DFX_DEV_GEN_PCIE_CLK_SRC_MASK); |
| 135 | } |
| 136 | |
| 137 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 138 | /* RFU configurations - hard reset comphy */ |
| 139 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 140 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 141 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 142 | data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 143 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 144 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 145 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 146 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 147 | mask |= COMMON_PHY_PHY_MODE_MASK; |
| 148 | data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; |
| 149 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 150 | |
| 151 | /* release from hard reset */ |
| 152 | mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 153 | data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 154 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 155 | data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 156 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 157 | |
| 158 | /* Wait 1ms - until band gap and ref clock ready */ |
| 159 | mdelay(1); |
| 160 | /* Start comphy Configuration */ |
| 161 | debug("stage: Comphy configuration\n"); |
| 162 | /* Set PIPE soft reset */ |
| 163 | mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; |
| 164 | data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; |
| 165 | /* Set PHY datapath width mode for V0 */ |
| 166 | mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; |
| 167 | data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; |
| 168 | /* Set Data bus width USB mode for V0 */ |
| 169 | mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; |
| 170 | data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; |
| 171 | /* Set CORE_CLK output frequency for 250Mhz */ |
| 172 | mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; |
| 173 | data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; |
| 174 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); |
| 175 | /* Set PLL ready delay for 0x2 */ |
| 176 | data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; |
| 177 | mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; |
| 178 | if (pcie_width != 1) { |
| 179 | data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; |
| 180 | mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; |
| 181 | data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; |
| 182 | mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; |
| 183 | } |
| 184 | reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); |
| 185 | |
| 186 | /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ |
| 187 | data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; |
| 188 | mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; |
| 189 | if (pcie_width != 1) { |
| 190 | mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; |
| 191 | mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; |
| 192 | mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; |
| 193 | if (lane == 0) { |
| 194 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; |
| 195 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; |
| 196 | } else if (lane == (pcie_width - 1)) { |
| 197 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; |
| 198 | } |
| 199 | } |
| 200 | reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); |
| 201 | /* Config update polarity equalization */ |
| 202 | reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, |
| 203 | 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, |
| 204 | HPIPE_CFG_UPDATE_POLARITY_MASK); |
| 205 | /* Set PIPE version 4 to mode enable */ |
| 206 | reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, |
| 207 | 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, |
| 208 | HPIPE_DFE_CTRL_28_PIPE4_MASK); |
| 209 | /* TODO: check if pcie clock is output/input - for bringup use input*/ |
| 210 | /* Enable PIN clock 100M_125M */ |
| 211 | mask = 0; |
| 212 | data = 0; |
| 213 | /* Only if clock is output, configure the clock-source mux */ |
| 214 | if (pcie_clk) { |
| 215 | mask |= HPIPE_MISC_CLK100M_125M_MASK; |
| 216 | data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; |
| 217 | } |
| 218 | /* |
| 219 | * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz |
| 220 | * clock |
| 221 | */ |
| 222 | mask |= HPIPE_MISC_TXDCLK_2X_MASK; |
| 223 | data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; |
| 224 | /* Enable 500MHz Clock */ |
| 225 | mask |= HPIPE_MISC_CLK500_EN_MASK; |
| 226 | data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; |
| 227 | if (pcie_clk) { /* output */ |
| 228 | /* Set reference clock comes from group 1 */ |
| 229 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; |
| 230 | data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; |
| 231 | } else { |
| 232 | /* Set reference clock comes from group 2 */ |
| 233 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; |
| 234 | data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; |
| 235 | } |
Igal Liberman | 50dd09e | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 236 | mask |= HPIPE_MISC_ICP_FORCE_MASK; |
| 237 | data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 238 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); |
| 239 | if (pcie_clk) { /* output */ |
| 240 | /* Set reference frequcency select - 0x2 for 25MHz*/ |
| 241 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 242 | data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 243 | } else { |
| 244 | /* Set reference frequcency select - 0x0 for 100MHz*/ |
| 245 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 246 | data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 247 | } |
| 248 | /* Set PHY mode to PCIe */ |
| 249 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 250 | data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 251 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 252 | |
| 253 | /* ref clock alignment */ |
| 254 | if (pcie_width != 1) { |
| 255 | mask = HPIPE_LANE_ALIGN_OFF_MASK; |
| 256 | data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; |
| 257 | reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); |
| 258 | } |
| 259 | |
| 260 | /* |
| 261 | * Set the amount of time spent in the LoZ state - set for 0x7 only if |
| 262 | * the PCIe clock is output |
| 263 | */ |
| 264 | if (pcie_clk) { |
| 265 | reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, |
| 266 | 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, |
| 267 | HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); |
| 268 | } |
| 269 | |
| 270 | /* Set Maximal PHY Generation Setting(8Gbps) */ |
| 271 | mask = HPIPE_INTERFACE_GEN_MAX_MASK; |
| 272 | data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; |
Igal Liberman | 50dd09e | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 273 | /* Bypass frame detection and sync detection for RX DATA */ |
| 274 | mask = HPIPE_INTERFACE_DET_BYPASS_MASK; |
| 275 | data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 276 | /* Set Link Train Mode (Tx training control pins are used) */ |
| 277 | mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; |
| 278 | data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; |
| 279 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); |
| 280 | |
| 281 | /* Set Idle_sync enable */ |
| 282 | mask = HPIPE_PCIE_IDLE_SYNC_MASK; |
| 283 | data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; |
| 284 | /* Select bits for PCIE Gen3(32bit) */ |
| 285 | mask |= HPIPE_PCIE_SEL_BITS_MASK; |
| 286 | data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; |
| 287 | reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); |
| 288 | |
| 289 | /* Enable Tx_adapt_g1 */ |
| 290 | mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; |
| 291 | data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; |
| 292 | /* Enable Tx_adapt_gn1 */ |
| 293 | mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; |
| 294 | data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; |
| 295 | /* Disable Tx_adapt_g0 */ |
| 296 | mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; |
| 297 | data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; |
| 298 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); |
| 299 | |
| 300 | /* Set reg_tx_train_chk_init */ |
| 301 | mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; |
| 302 | data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; |
| 303 | /* Enable TX_COE_FM_PIN_PCIE3_EN */ |
| 304 | mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; |
| 305 | data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; |
| 306 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); |
| 307 | |
| 308 | debug("stage: TRx training parameters\n"); |
| 309 | /* Set Preset sweep configurations */ |
| 310 | mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; |
| 311 | data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; |
| 312 | |
| 313 | mask |= HPIPE_TX_NUM_OF_PRESET_MASK; |
| 314 | data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; |
| 315 | |
| 316 | mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; |
| 317 | data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; |
| 318 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); |
| 319 | |
| 320 | /* Tx train start configuration */ |
| 321 | mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; |
| 322 | data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; |
| 323 | |
| 324 | mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; |
| 325 | data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; |
| 326 | |
| 327 | mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; |
| 328 | data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; |
| 329 | |
| 330 | mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; |
| 331 | data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; |
| 332 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); |
| 333 | |
| 334 | /* Enable Tx train P2P */ |
| 335 | mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; |
| 336 | data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; |
| 337 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); |
| 338 | |
| 339 | /* Configure Tx train timeout */ |
| 340 | mask = HPIPE_TRX_TRAIN_TIMER_MASK; |
| 341 | data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; |
| 342 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); |
| 343 | |
| 344 | /* Disable G0/G1/GN1 adaptation */ |
| 345 | mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK |
| 346 | | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; |
| 347 | data = 0; |
| 348 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); |
| 349 | |
| 350 | /* Disable DTL frequency loop */ |
| 351 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; |
| 352 | data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; |
| 353 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); |
| 354 | |
| 355 | /* Configure G3 DFE */ |
| 356 | mask = HPIPE_G3_DFE_RES_MASK; |
| 357 | data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; |
| 358 | reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); |
| 359 | |
Igal Liberman | 50dd09e | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 360 | /* Use TX/RX training result for DFE */ |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 361 | mask = HPIPE_DFE_RES_FORCE_MASK; |
Igal Liberman | 50dd09e | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 362 | data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 363 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); |
| 364 | |
| 365 | /* Configure initial and final coefficient value for receiver */ |
Igal Liberman | 547a98f | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 366 | mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; |
| 367 | data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 368 | |
Igal Liberman | 547a98f | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 369 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; |
| 370 | data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 371 | |
Igal Liberman | 547a98f | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 372 | mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; |
| 373 | data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; |
| 374 | reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 375 | |
| 376 | /* Trigger sampler enable pulse */ |
| 377 | mask = HPIPE_SMAPLER_MASK; |
| 378 | data = 0x1 << HPIPE_SMAPLER_OFFSET; |
| 379 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); |
| 380 | udelay(5); |
| 381 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); |
| 382 | |
| 383 | /* FFE resistor tuning for different bandwidth */ |
| 384 | mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; |
| 385 | data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; |
| 386 | |
| 387 | mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; |
Igal Liberman | 50dd09e | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 388 | data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 389 | reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); |
| 390 | |
Igal Liberman | 50dd09e | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 391 | /* Pattern lock lost timeout disable */ |
| 392 | mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; |
| 393 | data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; |
| 394 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); |
| 395 | |
| 396 | /* Configure DFE adaptations */ |
| 397 | mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; |
| 398 | data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; |
| 399 | mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; |
| 400 | data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; |
| 401 | mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; |
| 402 | data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; |
| 403 | reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); |
| 404 | mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; |
| 405 | data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; |
| 406 | reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); |
| 407 | |
| 408 | /* Genration 2 setting 1*/ |
| 409 | mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; |
| 410 | data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; |
| 411 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; |
| 412 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; |
| 413 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; |
| 414 | data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; |
| 415 | reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); |
| 416 | |
| 417 | /* DFE enable */ |
| 418 | mask = HPIPE_G2_DFE_RES_MASK; |
| 419 | data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; |
| 420 | reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); |
| 421 | |
| 422 | /* Configure DFE Resolution */ |
| 423 | mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; |
| 424 | data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; |
| 425 | reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); |
| 426 | |
| 427 | /* VDD calibration control */ |
| 428 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; |
| 429 | data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; |
| 430 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); |
| 431 | |
| 432 | /* Set PLL Charge-pump Current Control */ |
| 433 | mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; |
| 434 | data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; |
| 435 | reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); |
| 436 | |
| 437 | /* Set lane rqualization remote setting */ |
| 438 | mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; |
| 439 | data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; |
| 440 | mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; |
| 441 | data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; |
| 442 | mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; |
| 443 | data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; |
| 444 | reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); |
| 445 | |
Stefan Roese | 2313efe | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 446 | if (!is_end_point) { |
| 447 | /* Set phy in root complex mode */ |
| 448 | mask = HPIPE_CFG_PHY_RC_EP_MASK; |
| 449 | data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; |
| 450 | reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); |
| 451 | } |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 452 | |
| 453 | debug("stage: Comphy power up\n"); |
| 454 | |
| 455 | /* |
| 456 | * For PCIe by4 or by2 - release from reset only after finish to |
| 457 | * configure all lanes |
| 458 | */ |
| 459 | if ((pcie_width == 1) || (lane == (pcie_width - 1))) { |
| 460 | u32 i, start_lane, end_lane; |
| 461 | |
| 462 | if (pcie_width != 1) { |
| 463 | /* allows writing to all lanes in one write */ |
| 464 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 465 | 0x0 << |
| 466 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, |
| 467 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); |
| 468 | start_lane = 0; |
| 469 | end_lane = pcie_width; |
| 470 | |
| 471 | /* |
| 472 | * Release from PIPE soft reset |
| 473 | * for PCIe by4 or by2 - release from soft reset |
| 474 | * all lanes - can't use read modify write |
| 475 | */ |
| 476 | reg_set(HPIPE_ADDR(hpipe_base, 0) + |
| 477 | HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); |
| 478 | } else { |
| 479 | start_lane = lane; |
| 480 | end_lane = lane + 1; |
| 481 | |
| 482 | /* |
| 483 | * Release from PIPE soft reset |
| 484 | * for PCIe by4 or by2 - release from soft reset |
| 485 | * all lanes |
| 486 | */ |
| 487 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, |
| 488 | 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, |
| 489 | HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); |
| 490 | } |
| 491 | |
| 492 | |
| 493 | if (pcie_width != 1) { |
| 494 | /* disable writing to all lanes with one write */ |
| 495 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 496 | 0x3210 << |
| 497 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, |
| 498 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); |
| 499 | } |
| 500 | |
| 501 | debug("stage: Check PLL\n"); |
| 502 | /* Read lane status */ |
| 503 | for (i = start_lane; i < end_lane; i++) { |
| 504 | addr = HPIPE_ADDR(hpipe_base, i) + |
| 505 | HPIPE_LANE_STATUS1_REG; |
| 506 | data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; |
| 507 | mask = data; |
| 508 | data = polling_with_timeout(addr, data, mask, 15000); |
| 509 | if (data != 0) { |
| 510 | debug("Read from reg = %p - value = 0x%x\n", |
| 511 | hpipe_addr + HPIPE_LANE_STATUS1_REG, |
| 512 | data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 513 | pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 514 | ret = 0; |
| 515 | } |
| 516 | } |
| 517 | } |
| 518 | |
| 519 | debug_exit(); |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, |
| 524 | void __iomem *comphy_base) |
| 525 | { |
| 526 | u32 mask, data, ret = 1; |
| 527 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 528 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 529 | void __iomem *addr; |
| 530 | |
| 531 | debug_enter(); |
| 532 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 533 | /* RFU configurations - hard reset comphy */ |
| 534 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 535 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 536 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 537 | data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 538 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 539 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 540 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 541 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 542 | mask |= COMMON_PHY_PHY_MODE_MASK; |
| 543 | data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; |
| 544 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 545 | |
| 546 | /* release from hard reset */ |
| 547 | mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 548 | data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 549 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 550 | data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 551 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 552 | |
| 553 | /* Wait 1ms - until band gap and ref clock ready */ |
| 554 | mdelay(1); |
| 555 | |
| 556 | /* Start comphy Configuration */ |
| 557 | debug("stage: Comphy configuration\n"); |
| 558 | /* Set PIPE soft reset */ |
| 559 | mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; |
| 560 | data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; |
| 561 | /* Set PHY datapath width mode for V0 */ |
| 562 | mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; |
| 563 | data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; |
| 564 | /* Set Data bus width USB mode for V0 */ |
| 565 | mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; |
| 566 | data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; |
| 567 | /* Set CORE_CLK output frequency for 250Mhz */ |
| 568 | mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; |
| 569 | data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; |
| 570 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); |
| 571 | /* Set PLL ready delay for 0x2 */ |
| 572 | reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, |
| 573 | 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, |
| 574 | HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); |
| 575 | /* Set reference clock to come from group 1 - 25Mhz */ |
| 576 | reg_set(hpipe_addr + HPIPE_MISC_REG, |
| 577 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, |
| 578 | HPIPE_MISC_REFCLK_SEL_MASK); |
| 579 | /* Set reference frequcency select - 0x2 */ |
| 580 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 581 | data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 582 | /* Set PHY mode to USB - 0x5 */ |
| 583 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 584 | data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 585 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 586 | /* Set the amount of time spent in the LoZ state - set for 0x7 */ |
| 587 | reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, |
| 588 | 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, |
| 589 | HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); |
| 590 | /* Set max PHY generation setting - 5Gbps */ |
| 591 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, |
| 592 | 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, |
| 593 | HPIPE_INTERFACE_GEN_MAX_MASK); |
| 594 | /* Set select data width 20Bit (SEL_BITS[2:0]) */ |
| 595 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, |
| 596 | 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, |
| 597 | HPIPE_LOOPBACK_SEL_MASK); |
| 598 | /* select de-emphasize 3.5db */ |
| 599 | reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, |
| 600 | 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, |
| 601 | HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); |
| 602 | /* override tx margining from the MAC */ |
| 603 | reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, |
| 604 | 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, |
| 605 | HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); |
| 606 | |
| 607 | /* Start analog paramters from ETP(HW) */ |
| 608 | debug("stage: Analog paramters from ETP(HW)\n"); |
| 609 | /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ |
| 610 | mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; |
| 611 | data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; |
| 612 | /* Set Override PHY DFE control pins for 0x1 */ |
| 613 | mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; |
| 614 | data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; |
| 615 | /* Set Spread Spectrum Clock Enable fot 0x1 */ |
| 616 | mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; |
| 617 | data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; |
| 618 | reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); |
| 619 | /* End of analog parameters */ |
| 620 | |
| 621 | debug("stage: Comphy power up\n"); |
| 622 | /* Release from PIPE soft reset */ |
| 623 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, |
| 624 | 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, |
| 625 | HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); |
| 626 | |
| 627 | /* wait 15ms - for comphy calibration done */ |
| 628 | debug("stage: Check PLL\n"); |
| 629 | /* Read lane status */ |
| 630 | addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; |
| 631 | data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; |
| 632 | mask = data; |
| 633 | data = polling_with_timeout(addr, data, mask, 15000); |
| 634 | if (data != 0) { |
| 635 | debug("Read from reg = %p - value = 0x%x\n", |
| 636 | hpipe_addr + HPIPE_LANE_STATUS1_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 637 | pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 638 | ret = 0; |
| 639 | } |
| 640 | |
| 641 | debug_exit(); |
| 642 | return ret; |
| 643 | } |
| 644 | |
| 645 | static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, |
Rabeeh Khoury | 320bd15 | 2018-09-06 12:37:48 +0300 | [diff] [blame] | 646 | void __iomem *comphy_base, int cp_index, |
| 647 | u32 invert) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 648 | { |
| 649 | u32 mask, data, i, ret = 1; |
| 650 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 651 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); |
| 652 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 653 | void __iomem *addr; |
| 654 | void __iomem *sata_base = NULL; |
| 655 | int sata_node = -1; /* Set to -1 in order to read the first sata node */ |
| 656 | |
| 657 | debug_enter(); |
| 658 | |
| 659 | /* |
| 660 | * Assumption - each CP has only one SATA controller |
| 661 | * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 |
| 662 | * will return the first node always. |
| 663 | * In order to parse each CPs SATA node, fdt_node_offset_by_compatible |
| 664 | * must be called again (according to the CP id) |
| 665 | */ |
Igal Liberman | c8855ce | 2017-04-24 18:45:32 +0300 | [diff] [blame] | 666 | for (i = 0; i < (cp_index + 1); i++) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 667 | sata_node = fdt_node_offset_by_compatible( |
| 668 | gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); |
| 669 | |
| 670 | if (sata_node == 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 671 | pr_err("SATA node not found in FDT\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 672 | return 0; |
| 673 | } |
| 674 | |
| 675 | sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 676 | gd->fdt_blob, sata_node, "reg", 0, NULL, true); |
| 677 | if (sata_base == NULL) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 678 | pr_err("SATA address not found in FDT\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 679 | return 0; |
| 680 | } |
| 681 | |
| 682 | debug("SATA address found in FDT %p\n", sata_base); |
| 683 | |
| 684 | debug("stage: MAC configuration - power down comphy\n"); |
| 685 | /* |
| 686 | * MAC configuration powe down comphy use indirect address for |
| 687 | * vendor spesific SATA control register |
| 688 | */ |
| 689 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 690 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 691 | SATA3_VENDOR_ADDR_MASK); |
| 692 | /* SATA 0 power down */ |
| 693 | mask = SATA3_CTRL_SATA0_PD_MASK; |
| 694 | data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; |
| 695 | /* SATA 1 power down */ |
| 696 | mask |= SATA3_CTRL_SATA1_PD_MASK; |
| 697 | data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; |
| 698 | /* SATA SSU disable */ |
| 699 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; |
| 700 | data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; |
| 701 | /* SATA port 1 disable */ |
| 702 | mask |= SATA3_CTRL_SATA_SSU_MASK; |
| 703 | data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; |
| 704 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); |
| 705 | |
| 706 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 707 | /* RFU configurations - hard reset comphy */ |
| 708 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 709 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 710 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 711 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 712 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 713 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 714 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 715 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 716 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 717 | |
| 718 | /* Set select data width 40Bit - SATA mode only */ |
| 719 | reg_set(comphy_addr + COMMON_PHY_CFG6_REG, |
| 720 | 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, |
| 721 | COMMON_PHY_CFG6_IF_40_SEL_MASK); |
| 722 | |
| 723 | /* release from hard reset in SD external */ |
| 724 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 725 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 726 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 727 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 728 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 729 | |
| 730 | /* Wait 1ms - until band gap and ref clock ready */ |
| 731 | mdelay(1); |
| 732 | |
| 733 | debug("stage: Comphy configuration\n"); |
| 734 | /* Start comphy Configuration */ |
| 735 | /* Set reference clock to comes from group 1 - choose 25Mhz */ |
| 736 | reg_set(hpipe_addr + HPIPE_MISC_REG, |
| 737 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, |
| 738 | HPIPE_MISC_REFCLK_SEL_MASK); |
| 739 | /* Reference frequency select set 1 (for SATA = 25Mhz) */ |
| 740 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 741 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 742 | /* PHY mode select (set SATA = 0x0 */ |
| 743 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 744 | data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 745 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 746 | /* Set max PHY generation setting - 6Gbps */ |
| 747 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, |
| 748 | 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, |
| 749 | HPIPE_INTERFACE_GEN_MAX_MASK); |
| 750 | /* Set select data width 40Bit (SEL_BITS[2:0]) */ |
| 751 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, |
| 752 | 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); |
| 753 | |
| 754 | debug("stage: Analog paramters from ETP(HW)\n"); |
Igal Liberman | 547a98f | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 755 | /* Set analog parameters from ETP(HW) */ |
| 756 | /* G1 settings */ |
| 757 | mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; |
| 758 | data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; |
| 759 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; |
| 760 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; |
| 761 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; |
| 762 | data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; |
| 763 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; |
| 764 | data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; |
| 765 | mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; |
| 766 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; |
| 767 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); |
| 768 | |
| 769 | mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; |
| 770 | data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; |
| 771 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; |
| 772 | data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; |
| 773 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; |
| 774 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; |
| 775 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; |
| 776 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; |
| 777 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; |
| 778 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; |
| 779 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); |
| 780 | |
| 781 | /* G2 settings */ |
| 782 | mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; |
| 783 | data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; |
| 784 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; |
| 785 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; |
| 786 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; |
| 787 | data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; |
| 788 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; |
| 789 | data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; |
| 790 | mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; |
| 791 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; |
| 792 | reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); |
| 793 | |
| 794 | /* G3 settings */ |
| 795 | mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; |
| 796 | data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; |
| 797 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; |
| 798 | data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; |
| 799 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; |
| 800 | data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; |
| 801 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; |
| 802 | data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; |
| 803 | mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; |
| 804 | data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; |
| 805 | mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; |
| 806 | data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; |
| 807 | mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; |
| 808 | data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; |
| 809 | reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); |
| 810 | |
| 811 | /* DTL Control */ |
| 812 | mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; |
| 813 | data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; |
| 814 | mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; |
| 815 | data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; |
| 816 | mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; |
| 817 | data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; |
| 818 | mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; |
| 819 | data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; |
| 820 | mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; |
| 821 | data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; |
| 822 | mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; |
| 823 | data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; |
| 824 | mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; |
| 825 | data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; |
| 826 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); |
| 827 | |
| 828 | /* Trigger sampler enable pulse (by toggleing the bit) */ |
| 829 | mask = HPIPE_SMAPLER_MASK; |
| 830 | data = 0x1 << HPIPE_SMAPLER_OFFSET; |
| 831 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); |
| 832 | mask = HPIPE_SMAPLER_MASK; |
| 833 | data = 0x0 << HPIPE_SMAPLER_OFFSET; |
| 834 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); |
| 835 | |
| 836 | /* VDD Calibration Control 3 */ |
| 837 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; |
| 838 | data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; |
| 839 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); |
| 840 | |
| 841 | /* DFE Resolution Control */ |
| 842 | mask = HPIPE_DFE_RES_FORCE_MASK; |
| 843 | data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; |
| 844 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); |
| 845 | |
| 846 | /* DFE F3-F5 Coefficient Control */ |
| 847 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; |
| 848 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; |
| 849 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; |
| 850 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; |
| 851 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); |
| 852 | |
| 853 | /* G3 Setting 3 */ |
| 854 | mask = HPIPE_G3_FFE_CAP_SEL_MASK; |
| 855 | data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; |
| 856 | mask |= HPIPE_G3_FFE_RES_SEL_MASK; |
| 857 | data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; |
| 858 | mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; |
| 859 | data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; |
| 860 | mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; |
| 861 | data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; |
| 862 | mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; |
| 863 | data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; |
| 864 | reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); |
| 865 | |
| 866 | /* G3 Setting 4 */ |
| 867 | mask = HPIPE_G3_DFE_RES_MASK; |
| 868 | data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; |
| 869 | reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); |
| 870 | |
| 871 | /* Offset Phase Control */ |
| 872 | mask = HPIPE_OS_PH_OFFSET_MASK; |
| 873 | data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; |
| 874 | mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; |
| 875 | data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; |
| 876 | reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); |
| 877 | mask = HPIPE_OS_PH_VALID_MASK; |
| 878 | data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; |
| 879 | reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); |
| 880 | mask = HPIPE_OS_PH_VALID_MASK; |
| 881 | data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; |
| 882 | reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); |
| 883 | |
| 884 | /* Set G1 TX amplitude and TX post emphasis value */ |
| 885 | mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; |
| 886 | data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; |
| 887 | mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; |
| 888 | data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; |
| 889 | mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; |
| 890 | data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; |
| 891 | mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; |
| 892 | data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; |
| 893 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); |
| 894 | |
| 895 | /* Set G2 TX amplitude and TX post emphasis value */ |
| 896 | mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; |
| 897 | data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; |
| 898 | mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; |
| 899 | data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; |
| 900 | mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; |
| 901 | data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; |
| 902 | mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; |
| 903 | data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; |
| 904 | reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); |
| 905 | |
| 906 | /* Set G3 TX amplitude and TX post emphasis value */ |
| 907 | mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; |
| 908 | data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; |
| 909 | mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; |
| 910 | data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; |
| 911 | mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; |
| 912 | data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; |
| 913 | mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; |
| 914 | data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; |
| 915 | mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; |
| 916 | data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; |
| 917 | mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; |
| 918 | data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; |
| 919 | reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); |
| 920 | |
| 921 | /* SERDES External Configuration 2 register */ |
| 922 | mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; |
| 923 | data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; |
| 924 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 925 | |
| 926 | /* DFE reset sequence */ |
| 927 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, |
| 928 | 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, |
| 929 | HPIPE_PWR_CTR_RST_DFE_MASK); |
| 930 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, |
| 931 | 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, |
| 932 | HPIPE_PWR_CTR_RST_DFE_MASK); |
Rabeeh Khoury | 320bd15 | 2018-09-06 12:37:48 +0300 | [diff] [blame] | 933 | |
| 934 | /* Set RX / TX swaps */ |
| 935 | data = mask = 0; |
| 936 | if (invert & PHY_POLARITY_TXD_INVERT) { |
| 937 | data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET); |
| 938 | mask |= HPIPE_SYNC_PATTERN_TXD_SWAP_MASK; |
| 939 | } |
| 940 | if (invert & PHY_POLARITY_RXD_INVERT) { |
| 941 | data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET); |
| 942 | mask |= HPIPE_SYNC_PATTERN_RXD_SWAP_MASK; |
| 943 | } |
| 944 | reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask); |
| 945 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 946 | /* SW reset for interupt logic */ |
| 947 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, |
| 948 | 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, |
| 949 | HPIPE_PWR_CTR_SFT_RST_MASK); |
| 950 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, |
| 951 | 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, |
| 952 | HPIPE_PWR_CTR_SFT_RST_MASK); |
| 953 | |
| 954 | debug("stage: Comphy power up\n"); |
| 955 | /* |
| 956 | * MAC configuration power up comphy - power up PLL/TX/RX |
| 957 | * use indirect address for vendor spesific SATA control register |
| 958 | */ |
| 959 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 960 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 961 | SATA3_VENDOR_ADDR_MASK); |
| 962 | /* SATA 0 power up */ |
| 963 | mask = SATA3_CTRL_SATA0_PD_MASK; |
| 964 | data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; |
| 965 | /* SATA 1 power up */ |
| 966 | mask |= SATA3_CTRL_SATA1_PD_MASK; |
| 967 | data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; |
| 968 | /* SATA SSU enable */ |
| 969 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; |
| 970 | data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; |
| 971 | /* SATA port 1 enable */ |
| 972 | mask |= SATA3_CTRL_SATA_SSU_MASK; |
| 973 | data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; |
| 974 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); |
| 975 | |
| 976 | /* MBUS request size and interface select register */ |
| 977 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 978 | SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 979 | SATA3_VENDOR_ADDR_MASK); |
| 980 | /* Mbus regret enable */ |
| 981 | reg_set(sata_base + SATA3_VENDOR_DATA, |
| 982 | 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); |
| 983 | |
| 984 | debug("stage: Check PLL\n"); |
| 985 | |
| 986 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 987 | data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & |
| 988 | SD_EXTERNAL_STATUS0_PLL_RX_MASK; |
| 989 | mask = data; |
| 990 | data = polling_with_timeout(addr, data, mask, 15000); |
| 991 | if (data != 0) { |
| 992 | debug("Read from reg = %p - value = 0x%x\n", |
| 993 | hpipe_addr + HPIPE_LANE_STATUS1_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 994 | pr_err("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 995 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), |
| 996 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); |
| 997 | ret = 0; |
| 998 | } |
| 999 | |
| 1000 | debug_exit(); |
| 1001 | return ret; |
| 1002 | } |
| 1003 | |
| 1004 | static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, |
| 1005 | void __iomem *hpipe_base, |
| 1006 | void __iomem *comphy_base) |
| 1007 | { |
| 1008 | u32 mask, data, ret = 1; |
| 1009 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 1010 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); |
| 1011 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 1012 | void __iomem *addr; |
| 1013 | |
| 1014 | debug_enter(); |
| 1015 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 1016 | /* RFU configurations - hard reset comphy */ |
| 1017 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 1018 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 1019 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 1020 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 1021 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 1022 | |
| 1023 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ |
| 1024 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 1025 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 1026 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; |
| 1027 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; |
| 1028 | if (sgmii_speed == PHY_SPEED_1_25G) { |
| 1029 | data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; |
| 1030 | data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; |
| 1031 | } else { |
| 1032 | /* 3.125G */ |
| 1033 | data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; |
| 1034 | data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; |
| 1035 | } |
| 1036 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 1037 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 1038 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 1039 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 1040 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; |
| 1041 | data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; |
| 1042 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 1043 | |
| 1044 | /* release from hard reset */ |
| 1045 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 1046 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 1047 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 1048 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 1049 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 1050 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 1051 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1052 | |
| 1053 | /* release from hard reset */ |
| 1054 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 1055 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 1056 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 1057 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 1058 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1059 | |
| 1060 | |
| 1061 | /* Wait 1ms - until band gap and ref clock ready */ |
| 1062 | mdelay(1); |
| 1063 | |
| 1064 | /* Start comphy Configuration */ |
| 1065 | debug("stage: Comphy configuration\n"); |
| 1066 | /* set reference clock */ |
| 1067 | mask = HPIPE_MISC_REFCLK_SEL_MASK; |
| 1068 | data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; |
| 1069 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); |
| 1070 | /* Power and PLL Control */ |
| 1071 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 1072 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 1073 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 1074 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 1075 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 1076 | /* Loopback register */ |
| 1077 | mask = HPIPE_LOOPBACK_SEL_MASK; |
| 1078 | data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; |
| 1079 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); |
| 1080 | /* rx control 1 */ |
| 1081 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; |
| 1082 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; |
| 1083 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; |
| 1084 | data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; |
| 1085 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); |
| 1086 | /* DTL Control */ |
| 1087 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; |
| 1088 | data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; |
| 1089 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); |
| 1090 | |
| 1091 | /* Set analog paramters from ETP(HW) - for now use the default datas */ |
| 1092 | debug("stage: Analog paramters from ETP(HW)\n"); |
| 1093 | |
| 1094 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, |
| 1095 | 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, |
| 1096 | HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); |
| 1097 | |
| 1098 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); |
| 1099 | /* SERDES External Configuration */ |
| 1100 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 1101 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 1102 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 1103 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 1104 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 1105 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 1106 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 1107 | |
| 1108 | /* check PLL rx & tx ready */ |
| 1109 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 1110 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | |
| 1111 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; |
| 1112 | mask = data; |
| 1113 | data = polling_with_timeout(addr, data, mask, 15000); |
| 1114 | if (data != 0) { |
| 1115 | debug("Read from reg = %p - value = 0x%x\n", |
| 1116 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1117 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1118 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
| 1119 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); |
| 1120 | ret = 0; |
| 1121 | } |
| 1122 | |
| 1123 | /* RX init */ |
| 1124 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; |
| 1125 | data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; |
| 1126 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1127 | |
| 1128 | /* check that RX init done */ |
| 1129 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 1130 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; |
| 1131 | mask = data; |
| 1132 | data = polling_with_timeout(addr, data, mask, 100); |
| 1133 | if (data != 0) { |
| 1134 | debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1135 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1136 | ret = 0; |
| 1137 | } |
| 1138 | |
| 1139 | debug("stage: RF Reset\n"); |
| 1140 | /* RF Reset */ |
| 1141 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; |
| 1142 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; |
| 1143 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 1144 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 1145 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1146 | |
| 1147 | debug_exit(); |
| 1148 | return ret; |
| 1149 | } |
| 1150 | |
Stefan Roese | db720b7 | 2017-04-24 18:45:21 +0300 | [diff] [blame] | 1151 | static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1152 | void __iomem *comphy_base, u32 speed) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1153 | { |
| 1154 | u32 mask, data, ret = 1; |
| 1155 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 1156 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); |
| 1157 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 1158 | void __iomem *addr; |
| 1159 | |
| 1160 | debug_enter(); |
| 1161 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 1162 | /* RFU configurations - hard reset comphy */ |
| 1163 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 1164 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 1165 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 1166 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 1167 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 1168 | |
| 1169 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ |
| 1170 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 1171 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 1172 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; |
| 1173 | data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; |
| 1174 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; |
| 1175 | data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; |
| 1176 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 1177 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 1178 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 1179 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 1180 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; |
| 1181 | data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; |
| 1182 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 1183 | |
| 1184 | /* release from hard reset */ |
| 1185 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 1186 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 1187 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 1188 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 1189 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 1190 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 1191 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1192 | |
| 1193 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 1194 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 1195 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 1196 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 1197 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1198 | |
| 1199 | |
| 1200 | /* Wait 1ms - until band gap and ref clock ready */ |
| 1201 | mdelay(1); |
| 1202 | |
| 1203 | /* Start comphy Configuration */ |
| 1204 | debug("stage: Comphy configuration\n"); |
| 1205 | /* set reference clock */ |
| 1206 | mask = HPIPE_MISC_ICP_FORCE_MASK; |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1207 | data = (speed == PHY_SPEED_5_15625G) ? |
| 1208 | (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : |
| 1209 | (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1210 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; |
| 1211 | data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; |
| 1212 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); |
| 1213 | /* Power and PLL Control */ |
| 1214 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 1215 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 1216 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 1217 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 1218 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 1219 | /* Loopback register */ |
| 1220 | mask = HPIPE_LOOPBACK_SEL_MASK; |
| 1221 | data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; |
| 1222 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); |
| 1223 | /* rx control 1 */ |
| 1224 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; |
| 1225 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; |
| 1226 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; |
| 1227 | data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; |
| 1228 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); |
| 1229 | /* DTL Control */ |
| 1230 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; |
| 1231 | data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; |
| 1232 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); |
| 1233 | |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1234 | /* Transmitter/Receiver Speed Divider Force */ |
| 1235 | if (speed == PHY_SPEED_5_15625G) { |
| 1236 | mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; |
| 1237 | data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; |
| 1238 | mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; |
| 1239 | data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; |
| 1240 | mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; |
| 1241 | data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; |
| 1242 | mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; |
| 1243 | data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; |
Igal Liberman | 980d809 | 2017-04-24 18:45:31 +0300 | [diff] [blame] | 1244 | } else { |
| 1245 | mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; |
| 1246 | data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1247 | } |
Igal Liberman | 980d809 | 2017-04-24 18:45:31 +0300 | [diff] [blame] | 1248 | reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1249 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1250 | /* Set analog paramters from ETP(HW) */ |
| 1251 | debug("stage: Analog paramters from ETP(HW)\n"); |
| 1252 | /* SERDES External Configuration 2 */ |
| 1253 | mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; |
| 1254 | data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; |
| 1255 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); |
| 1256 | /* 0x7-DFE Resolution control */ |
| 1257 | mask = HPIPE_DFE_RES_FORCE_MASK; |
| 1258 | data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; |
| 1259 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); |
| 1260 | /* 0xd-G1_Setting_0 */ |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1261 | if (speed == PHY_SPEED_5_15625G) { |
| 1262 | mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; |
| 1263 | data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; |
| 1264 | } else { |
| 1265 | mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; |
| 1266 | data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; |
| 1267 | mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; |
| 1268 | data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; |
| 1269 | } |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1270 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); |
| 1271 | /* Genration 1 setting 2 (G1_Setting_2) */ |
| 1272 | mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; |
| 1273 | data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; |
| 1274 | mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; |
| 1275 | data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; |
| 1276 | reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); |
| 1277 | /* Transmitter Slew Rate Control register (tx_reg1) */ |
| 1278 | mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; |
| 1279 | data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; |
| 1280 | mask |= HPIPE_TX_REG1_SLC_EN_MASK; |
| 1281 | data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; |
| 1282 | reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); |
| 1283 | /* Impedance Calibration Control register (cal_reg1) */ |
| 1284 | mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; |
| 1285 | data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; |
| 1286 | mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; |
| 1287 | data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; |
| 1288 | reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); |
| 1289 | /* Generation 1 Setting 5 (g1_setting_5) */ |
| 1290 | mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; |
| 1291 | data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; |
| 1292 | reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); |
| 1293 | /* 0xE-G1_Setting_1 */ |
Igal Liberman | 980d809 | 2017-04-24 18:45:31 +0300 | [diff] [blame] | 1294 | mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; |
| 1295 | data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; |
| 1296 | if (speed == PHY_SPEED_5_15625G) { |
| 1297 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; |
| 1298 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; |
| 1299 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; |
| 1300 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; |
| 1301 | } else { |
| 1302 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; |
| 1303 | data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; |
| 1304 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; |
| 1305 | data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; |
| 1306 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; |
| 1307 | data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; |
| 1308 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; |
| 1309 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; |
| 1310 | mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; |
| 1311 | data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; |
| 1312 | } |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1313 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); |
Igal Liberman | 980d809 | 2017-04-24 18:45:31 +0300 | [diff] [blame] | 1314 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1315 | /* 0xA-DFE_Reg3 */ |
| 1316 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; |
| 1317 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; |
| 1318 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; |
| 1319 | data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; |
| 1320 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); |
| 1321 | |
| 1322 | /* 0x111-G1_Setting_4 */ |
| 1323 | mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; |
| 1324 | data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; |
| 1325 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); |
| 1326 | /* Genration 1 setting 3 (G1_Setting_3) */ |
| 1327 | mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; |
| 1328 | data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 1329 | if (speed == PHY_SPEED_5_15625G) { |
| 1330 | /* Force FFE (Feed Forward Equalization) to 5G */ |
| 1331 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; |
| 1332 | data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; |
| 1333 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; |
| 1334 | data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; |
| 1335 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; |
| 1336 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; |
| 1337 | } |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1338 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); |
| 1339 | |
Igal Liberman | 980d809 | 2017-04-24 18:45:31 +0300 | [diff] [blame] | 1340 | /* Connfigure RX training timer */ |
| 1341 | mask = HPIPE_RX_TRAIN_TIMER_MASK; |
| 1342 | data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; |
| 1343 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); |
| 1344 | |
| 1345 | /* Enable TX train peak to peak hold */ |
| 1346 | mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; |
| 1347 | data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; |
| 1348 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); |
| 1349 | |
| 1350 | /* Configure TX preset index */ |
| 1351 | mask = HPIPE_TX_PRESET_INDEX_MASK; |
| 1352 | data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; |
| 1353 | reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); |
| 1354 | |
| 1355 | /* Disable pattern lock lost timeout */ |
| 1356 | mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; |
| 1357 | data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; |
| 1358 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); |
| 1359 | |
| 1360 | /* Configure TX training pattern and TX training 16bit auto */ |
| 1361 | mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; |
| 1362 | data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; |
| 1363 | mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; |
| 1364 | data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; |
| 1365 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); |
| 1366 | |
| 1367 | /* Configure Training patten number */ |
| 1368 | mask = HPIPE_TRAIN_PAT_NUM_MASK; |
| 1369 | data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; |
| 1370 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); |
| 1371 | |
| 1372 | /* Configure differencial manchester encoter to ethernet mode */ |
| 1373 | mask = HPIPE_DME_ETHERNET_MODE_MASK; |
| 1374 | data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; |
| 1375 | reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); |
| 1376 | |
| 1377 | /* Configure VDD Continuous Calibration */ |
| 1378 | mask = HPIPE_CAL_VDD_CONT_MODE_MASK; |
| 1379 | data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; |
| 1380 | reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); |
| 1381 | |
| 1382 | /* Trigger sampler enable pulse (by toggleing the bit) */ |
| 1383 | mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; |
| 1384 | data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; |
| 1385 | mask |= HPIPE_SMAPLER_MASK; |
| 1386 | data |= 0x1 << HPIPE_SMAPLER_OFFSET; |
| 1387 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); |
| 1388 | mask = HPIPE_SMAPLER_MASK; |
| 1389 | data = 0x0 << HPIPE_SMAPLER_OFFSET; |
| 1390 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); |
| 1391 | |
| 1392 | /* Set External RX Regulator Control */ |
| 1393 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; |
| 1394 | data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; |
| 1395 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); |
| 1396 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1397 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); |
| 1398 | /* SERDES External Configuration */ |
| 1399 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 1400 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 1401 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 1402 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 1403 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 1404 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 1405 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 1406 | |
| 1407 | |
| 1408 | /* check PLL rx & tx ready */ |
| 1409 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 1410 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | |
| 1411 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; |
| 1412 | mask = data; |
| 1413 | data = polling_with_timeout(addr, data, mask, 15000); |
| 1414 | if (data != 0) { |
| 1415 | debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1416 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1417 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
| 1418 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); |
| 1419 | ret = 0; |
| 1420 | } |
| 1421 | |
| 1422 | /* RX init */ |
| 1423 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; |
| 1424 | data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; |
| 1425 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1426 | |
| 1427 | |
| 1428 | /* check that RX init done */ |
| 1429 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 1430 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; |
| 1431 | mask = data; |
| 1432 | data = polling_with_timeout(addr, data, mask, 100); |
| 1433 | if (data != 0) { |
| 1434 | debug("Read from reg = %p - value = 0x%x\n", |
| 1435 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1436 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1437 | ret = 0; |
| 1438 | } |
| 1439 | |
| 1440 | debug("stage: RF Reset\n"); |
| 1441 | /* RF Reset */ |
| 1442 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; |
| 1443 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; |
| 1444 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 1445 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 1446 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1447 | |
| 1448 | debug_exit(); |
| 1449 | return ret; |
| 1450 | } |
| 1451 | |
| 1452 | static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, |
| 1453 | void __iomem *comphy_base) |
| 1454 | { |
| 1455 | u32 mask, data, ret = 1; |
| 1456 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 1457 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); |
| 1458 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 1459 | void __iomem *addr; |
| 1460 | |
| 1461 | debug_enter(); |
| 1462 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 1463 | /* RFU configurations - hard reset comphy */ |
| 1464 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 1465 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 1466 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 1467 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 1468 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 1469 | |
| 1470 | if (lane == 2) { |
| 1471 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 1472 | 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, |
| 1473 | COMMON_PHY_SD_CTRL1_RXAUI0_MASK); |
| 1474 | } |
| 1475 | if (lane == 4) { |
| 1476 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 1477 | 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, |
| 1478 | COMMON_PHY_SD_CTRL1_RXAUI1_MASK); |
| 1479 | } |
| 1480 | |
| 1481 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ |
| 1482 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 1483 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 1484 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; |
| 1485 | data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; |
| 1486 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; |
| 1487 | data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; |
| 1488 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 1489 | data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 1490 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 1491 | data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 1492 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; |
| 1493 | data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; |
| 1494 | mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; |
| 1495 | data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; |
| 1496 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 1497 | |
| 1498 | /* release from hard reset */ |
| 1499 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 1500 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 1501 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 1502 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 1503 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 1504 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 1505 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1506 | |
| 1507 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 1508 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 1509 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 1510 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 1511 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1512 | |
| 1513 | /* Wait 1ms - until band gap and ref clock ready */ |
| 1514 | mdelay(1); |
| 1515 | |
| 1516 | /* Start comphy Configuration */ |
| 1517 | debug("stage: Comphy configuration\n"); |
| 1518 | /* set reference clock */ |
| 1519 | reg_set(hpipe_addr + HPIPE_MISC_REG, |
| 1520 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, |
| 1521 | HPIPE_MISC_REFCLK_SEL_MASK); |
| 1522 | /* Power and PLL Control */ |
| 1523 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 1524 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 1525 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 1526 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 1527 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 1528 | /* Loopback register */ |
| 1529 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, |
| 1530 | 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); |
| 1531 | /* rx control 1 */ |
| 1532 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; |
| 1533 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; |
| 1534 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; |
| 1535 | data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; |
| 1536 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); |
| 1537 | /* DTL Control */ |
| 1538 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, |
| 1539 | 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, |
| 1540 | HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); |
| 1541 | |
| 1542 | /* Set analog paramters from ETP(HW) */ |
| 1543 | debug("stage: Analog paramters from ETP(HW)\n"); |
| 1544 | /* SERDES External Configuration 2 */ |
| 1545 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, |
| 1546 | 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, |
| 1547 | SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); |
| 1548 | /* 0x7-DFE Resolution control */ |
| 1549 | reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, |
| 1550 | HPIPE_DFE_RES_FORCE_MASK); |
| 1551 | /* 0xd-G1_Setting_0 */ |
| 1552 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, |
| 1553 | 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, |
| 1554 | HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); |
| 1555 | /* 0xE-G1_Setting_1 */ |
| 1556 | mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; |
| 1557 | data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; |
| 1558 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; |
| 1559 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; |
| 1560 | mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; |
| 1561 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; |
| 1562 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); |
| 1563 | /* 0xA-DFE_Reg3 */ |
| 1564 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; |
| 1565 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; |
| 1566 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; |
| 1567 | data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; |
| 1568 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); |
| 1569 | |
| 1570 | /* 0x111-G1_Setting_4 */ |
| 1571 | mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; |
| 1572 | data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; |
| 1573 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); |
| 1574 | |
| 1575 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); |
| 1576 | /* SERDES External Configuration */ |
| 1577 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 1578 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 1579 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 1580 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 1581 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 1582 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 1583 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 1584 | |
| 1585 | |
| 1586 | /* check PLL rx & tx ready */ |
| 1587 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 1588 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | |
| 1589 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; |
| 1590 | mask = data; |
| 1591 | data = polling_with_timeout(addr, data, mask, 15000); |
| 1592 | if (data != 0) { |
| 1593 | debug("Read from reg = %p - value = 0x%x\n", |
| 1594 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1595 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1596 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
| 1597 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); |
| 1598 | ret = 0; |
| 1599 | } |
| 1600 | |
| 1601 | /* RX init */ |
| 1602 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, |
| 1603 | 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, |
| 1604 | SD_EXTERNAL_CONFIG1_RX_INIT_MASK); |
| 1605 | |
| 1606 | /* check that RX init done */ |
| 1607 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 1608 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; |
| 1609 | mask = data; |
| 1610 | data = polling_with_timeout(addr, data, mask, 100); |
| 1611 | if (data != 0) { |
| 1612 | debug("Read from reg = %p - value = 0x%x\n", |
| 1613 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1614 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1615 | ret = 0; |
| 1616 | } |
| 1617 | |
| 1618 | debug("stage: RF Reset\n"); |
| 1619 | /* RF Reset */ |
| 1620 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; |
| 1621 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; |
| 1622 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 1623 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 1624 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 1625 | |
| 1626 | debug_exit(); |
| 1627 | return ret; |
| 1628 | } |
| 1629 | |
| 1630 | static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, |
| 1631 | void __iomem *usb_cfg_addr, |
| 1632 | void __iomem *utmi_cfg_addr, |
| 1633 | u32 utmi_phy_port) |
| 1634 | { |
| 1635 | u32 mask, data; |
| 1636 | |
| 1637 | debug_enter(); |
| 1638 | debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", |
| 1639 | utmi_index); |
| 1640 | /* Power down UTMI PHY */ |
| 1641 | reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, |
| 1642 | UTMI_PHY_CFG_PU_MASK); |
| 1643 | |
| 1644 | /* |
| 1645 | * If UTMI connected to USB Device, configure mux prior to PHY init |
| 1646 | * (Device can be connected to UTMI0 or to UTMI1) |
| 1647 | */ |
Stefan Roese | b781f57 | 2017-04-24 18:45:23 +0300 | [diff] [blame] | 1648 | if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1649 | debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", |
| 1650 | utmi_index); |
| 1651 | /* USB3 Device UTMI enable */ |
| 1652 | mask = UTMI_USB_CFG_DEVICE_EN_MASK; |
| 1653 | data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; |
| 1654 | /* USB3 Device UTMI MUX */ |
| 1655 | mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; |
| 1656 | data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; |
| 1657 | reg_set(usb_cfg_addr, data, mask); |
| 1658 | } |
| 1659 | |
| 1660 | /* Set Test suspendm mode */ |
| 1661 | mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; |
| 1662 | data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; |
| 1663 | /* Enable Test UTMI select */ |
| 1664 | mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; |
| 1665 | data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; |
| 1666 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); |
| 1667 | |
| 1668 | /* Wait for UTMI power down */ |
| 1669 | mdelay(1); |
| 1670 | |
| 1671 | debug_exit(); |
| 1672 | return; |
| 1673 | } |
| 1674 | |
| 1675 | static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, |
| 1676 | void __iomem *usb_cfg_addr, |
| 1677 | void __iomem *utmi_cfg_addr, |
| 1678 | u32 utmi_phy_port) |
| 1679 | { |
| 1680 | u32 mask, data; |
| 1681 | |
| 1682 | debug_exit(); |
| 1683 | debug("stage: Configure UTMI PHY %d registers\n", utmi_index); |
| 1684 | /* Reference Clock Divider Select */ |
| 1685 | mask = UTMI_PLL_CTRL_REFDIV_MASK; |
| 1686 | data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; |
| 1687 | /* Feedback Clock Divider Select - 90 for 25Mhz*/ |
| 1688 | mask |= UTMI_PLL_CTRL_FBDIV_MASK; |
| 1689 | data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; |
| 1690 | /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ |
| 1691 | mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; |
| 1692 | data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; |
| 1693 | reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); |
| 1694 | |
| 1695 | /* Impedance Calibration Threshold Setting */ |
| 1696 | reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, |
| 1697 | 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, |
| 1698 | UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); |
| 1699 | |
| 1700 | /* Set LS TX driver strength coarse control */ |
| 1701 | mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; |
| 1702 | data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; |
| 1703 | /* Set LS TX driver fine adjustment */ |
| 1704 | mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; |
| 1705 | data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; |
| 1706 | reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); |
| 1707 | |
| 1708 | /* Enable SQ */ |
| 1709 | mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; |
| 1710 | data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; |
| 1711 | /* Enable analog squelch detect */ |
| 1712 | mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; |
| 1713 | data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; |
| 1714 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); |
| 1715 | |
| 1716 | /* Set External squelch calibration number */ |
| 1717 | mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; |
| 1718 | data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; |
| 1719 | /* Enable the External squelch calibration */ |
| 1720 | mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; |
| 1721 | data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; |
| 1722 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); |
| 1723 | |
| 1724 | /* Set Control VDAT Reference Voltage - 0.325V */ |
| 1725 | mask = UTMI_CHGDTC_CTRL_VDAT_MASK; |
| 1726 | data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; |
| 1727 | /* Set Control VSRC Reference Voltage - 0.6V */ |
| 1728 | mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; |
| 1729 | data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; |
| 1730 | reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); |
| 1731 | |
| 1732 | debug_exit(); |
| 1733 | return; |
| 1734 | } |
| 1735 | |
| 1736 | static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, |
| 1737 | void __iomem *usb_cfg_addr, |
| 1738 | void __iomem *utmi_cfg_addr, u32 utmi_phy_port) |
| 1739 | { |
| 1740 | u32 data, mask, ret = 1; |
| 1741 | void __iomem *addr; |
| 1742 | |
| 1743 | debug_enter(); |
| 1744 | debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", |
| 1745 | utmi_index); |
| 1746 | /* Power UP UTMI PHY */ |
| 1747 | reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, |
| 1748 | UTMI_PHY_CFG_PU_MASK); |
| 1749 | /* Disable Test UTMI select */ |
| 1750 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, |
| 1751 | 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, |
| 1752 | UTMI_CTRL_STATUS0_TEST_SEL_MASK); |
| 1753 | |
| 1754 | debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); |
| 1755 | addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; |
| 1756 | data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; |
| 1757 | mask = data; |
| 1758 | data = polling_with_timeout(addr, data, mask, 100); |
| 1759 | if (data != 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1760 | pr_err("Impedance calibration is not done\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1761 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 1762 | ret = 0; |
| 1763 | } |
| 1764 | |
| 1765 | data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; |
| 1766 | mask = data; |
| 1767 | data = polling_with_timeout(addr, data, mask, 100); |
| 1768 | if (data != 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1769 | pr_err("PLL calibration is not done\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1770 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 1771 | ret = 0; |
| 1772 | } |
| 1773 | |
| 1774 | addr = utmi_base_addr + UTMI_PLL_CTRL_REG; |
| 1775 | data = UTMI_PLL_CTRL_PLL_RDY_MASK; |
| 1776 | mask = data; |
| 1777 | data = polling_with_timeout(addr, data, mask, 100); |
| 1778 | if (data != 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1779 | pr_err("PLL is not ready\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1780 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 1781 | ret = 0; |
| 1782 | } |
| 1783 | |
| 1784 | if (ret) |
| 1785 | debug("Passed\n"); |
| 1786 | else |
| 1787 | debug("\n"); |
| 1788 | |
| 1789 | debug_exit(); |
| 1790 | return ret; |
| 1791 | } |
| 1792 | |
| 1793 | /* |
| 1794 | * comphy_utmi_phy_init initialize the UTMI PHY |
| 1795 | * the init split in 3 parts: |
| 1796 | * 1. Power down transceiver and PLL |
| 1797 | * 2. UTMI PHY configure |
| 1798 | * 3. Powe up transceiver and PLL |
| 1799 | * Note: - Power down/up should be once for both UTMI PHYs |
| 1800 | * - comphy_dedicated_phys_init call this function if at least there is |
| 1801 | * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is |
| 1802 | * legal |
| 1803 | */ |
| 1804 | static void comphy_utmi_phy_init(u32 utmi_phy_count, |
| 1805 | struct utmi_phy_data *cp110_utmi_data) |
| 1806 | { |
| 1807 | u32 i; |
| 1808 | |
| 1809 | debug_enter(); |
| 1810 | /* UTMI Power down */ |
| 1811 | for (i = 0; i < utmi_phy_count; i++) { |
| 1812 | comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, |
| 1813 | cp110_utmi_data[i].usb_cfg_addr, |
| 1814 | cp110_utmi_data[i].utmi_cfg_addr, |
| 1815 | cp110_utmi_data[i].utmi_phy_port); |
| 1816 | } |
| 1817 | /* PLL Power down */ |
| 1818 | debug("stage: UTMI PHY power down PLL\n"); |
| 1819 | for (i = 0; i < utmi_phy_count; i++) { |
| 1820 | reg_set(cp110_utmi_data[i].usb_cfg_addr, |
| 1821 | 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); |
| 1822 | } |
| 1823 | /* UTMI configure */ |
| 1824 | for (i = 0; i < utmi_phy_count; i++) { |
| 1825 | comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, |
| 1826 | cp110_utmi_data[i].usb_cfg_addr, |
| 1827 | cp110_utmi_data[i].utmi_cfg_addr, |
| 1828 | cp110_utmi_data[i].utmi_phy_port); |
| 1829 | } |
| 1830 | /* UTMI Power up */ |
| 1831 | for (i = 0; i < utmi_phy_count; i++) { |
| 1832 | if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, |
| 1833 | cp110_utmi_data[i].usb_cfg_addr, |
| 1834 | cp110_utmi_data[i].utmi_cfg_addr, |
| 1835 | cp110_utmi_data[i].utmi_phy_port)) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1836 | pr_err("Failed to initialize UTMI PHY %d\n", i); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1837 | continue; |
| 1838 | } |
| 1839 | printf("UTMI PHY %d initialized to ", i); |
Stefan Roese | b781f57 | 2017-04-24 18:45:23 +0300 | [diff] [blame] | 1840 | if (cp110_utmi_data[i].utmi_phy_port == |
| 1841 | UTMI_PHY_TO_USB3_DEVICE0) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1842 | printf("USB Device\n"); |
| 1843 | else |
| 1844 | printf("USB Host%d\n", |
| 1845 | cp110_utmi_data[i].utmi_phy_port); |
| 1846 | } |
| 1847 | /* PLL Power up */ |
| 1848 | debug("stage: UTMI PHY power up PLL\n"); |
| 1849 | for (i = 0; i < utmi_phy_count; i++) { |
| 1850 | reg_set(cp110_utmi_data[i].usb_cfg_addr, |
| 1851 | 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); |
| 1852 | } |
| 1853 | |
| 1854 | debug_exit(); |
| 1855 | return; |
| 1856 | } |
| 1857 | |
| 1858 | /* |
| 1859 | * comphy_dedicated_phys_init initialize the dedicated PHYs |
| 1860 | * - not muxed SerDes lanes e.g. UTMI PHY |
| 1861 | */ |
| 1862 | void comphy_dedicated_phys_init(void) |
| 1863 | { |
| 1864 | struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; |
| 1865 | int node; |
| 1866 | int i; |
| 1867 | |
| 1868 | debug_enter(); |
| 1869 | debug("Initialize USB UTMI PHYs\n"); |
| 1870 | |
| 1871 | /* Find the UTMI phy node in device tree and go over them */ |
| 1872 | node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, |
| 1873 | "marvell,mvebu-utmi-2.6.0"); |
| 1874 | |
| 1875 | i = 0; |
| 1876 | while (node > 0) { |
| 1877 | /* get base address of UTMI phy */ |
| 1878 | cp110_utmi_data[i].utmi_base_addr = |
| 1879 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 1880 | gd->fdt_blob, node, "reg", 0, NULL, true); |
| 1881 | if (cp110_utmi_data[i].utmi_base_addr == NULL) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1882 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1883 | i++; |
| 1884 | continue; |
| 1885 | } |
| 1886 | |
| 1887 | /* get usb config address */ |
| 1888 | cp110_utmi_data[i].usb_cfg_addr = |
| 1889 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 1890 | gd->fdt_blob, node, "reg", 1, NULL, true); |
| 1891 | if (cp110_utmi_data[i].usb_cfg_addr == NULL) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1892 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1893 | i++; |
| 1894 | continue; |
| 1895 | } |
| 1896 | |
| 1897 | /* get UTMI config address */ |
| 1898 | cp110_utmi_data[i].utmi_cfg_addr = |
| 1899 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 1900 | gd->fdt_blob, node, "reg", 2, NULL, true); |
| 1901 | if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1902 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1903 | i++; |
| 1904 | continue; |
| 1905 | } |
| 1906 | |
| 1907 | /* |
| 1908 | * get the port number (to check if the utmi connected to |
| 1909 | * host/device) |
| 1910 | */ |
| 1911 | cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( |
| 1912 | gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); |
| 1913 | if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1914 | pr_err("UTMI PHY port type is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1915 | i++; |
| 1916 | continue; |
| 1917 | } |
| 1918 | |
| 1919 | node = fdt_node_offset_by_compatible( |
| 1920 | gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); |
| 1921 | i++; |
| 1922 | } |
| 1923 | |
| 1924 | if (i > 0) |
| 1925 | comphy_utmi_phy_init(i, cp110_utmi_data); |
| 1926 | |
| 1927 | debug_exit(); |
| 1928 | } |
| 1929 | |
| 1930 | static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, |
| 1931 | struct comphy_map *serdes_map) |
| 1932 | { |
| 1933 | void __iomem *comphy_base_addr; |
| 1934 | struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; |
| 1935 | struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; |
| 1936 | u32 lane, comphy_max_count; |
| 1937 | |
| 1938 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; |
| 1939 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; |
| 1940 | |
| 1941 | /* |
| 1942 | * Copy the SerDes map configuration for PIPE map and PHY map |
| 1943 | * the comphy_mux_init modify the type of the lane if the type |
| 1944 | * is not valid because we have 2 selectores run the |
| 1945 | * comphy_mux_init twice and after that update the original |
| 1946 | * serdes_map |
| 1947 | */ |
| 1948 | for (lane = 0; lane < comphy_max_count; lane++) { |
| 1949 | comphy_map_pipe_data[lane].type = serdes_map[lane].type; |
| 1950 | comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; |
| 1951 | comphy_map_phy_data[lane].type = serdes_map[lane].type; |
| 1952 | comphy_map_phy_data[lane].speed = serdes_map[lane].speed; |
| 1953 | } |
| 1954 | ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; |
| 1955 | comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, |
| 1956 | comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); |
| 1957 | |
| 1958 | ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; |
| 1959 | comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, |
| 1960 | comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); |
| 1961 | /* Fix the type after check the PHY and PIPE configuration */ |
| 1962 | for (lane = 0; lane < comphy_max_count; lane++) { |
| 1963 | if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && |
| 1964 | (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) |
| 1965 | serdes_map[lane].type = PHY_TYPE_UNCONNECTED; |
| 1966 | } |
| 1967 | } |
| 1968 | |
| 1969 | int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, |
| 1970 | struct comphy_map *serdes_map) |
| 1971 | { |
| 1972 | struct comphy_map *ptr_comphy_map; |
| 1973 | void __iomem *comphy_base_addr, *hpipe_base_addr; |
| 1974 | u32 comphy_max_count, lane, ret = 0; |
| 1975 | u32 pcie_width = 0; |
| 1976 | |
| 1977 | debug_enter(); |
| 1978 | |
| 1979 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; |
| 1980 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; |
| 1981 | hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; |
| 1982 | |
| 1983 | /* Config Comphy mux configuration */ |
| 1984 | comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); |
| 1985 | |
| 1986 | /* Check if the first 4 lanes configured as By-4 */ |
| 1987 | for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; |
| 1988 | lane++, ptr_comphy_map++) { |
| 1989 | if (ptr_comphy_map->type != PHY_TYPE_PEX0) |
| 1990 | break; |
| 1991 | pcie_width++; |
| 1992 | } |
| 1993 | |
| 1994 | for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; |
| 1995 | lane++, ptr_comphy_map++) { |
| 1996 | debug("Initialize serdes number %d\n", lane); |
| 1997 | debug("Serdes type = 0x%x\n", ptr_comphy_map->type); |
| 1998 | if (lane == 4) { |
| 1999 | /* |
| 2000 | * PCIe lanes above the first 4 lanes, can be only |
| 2001 | * by1 |
| 2002 | */ |
| 2003 | pcie_width = 1; |
| 2004 | } |
| 2005 | switch (ptr_comphy_map->type) { |
| 2006 | case PHY_TYPE_UNCONNECTED: |
Stefan Roese | f4fed5c | 2017-04-24 18:45:24 +0300 | [diff] [blame] | 2007 | case PHY_TYPE_IGNORE: |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2008 | continue; |
| 2009 | break; |
| 2010 | case PHY_TYPE_PEX0: |
| 2011 | case PHY_TYPE_PEX1: |
| 2012 | case PHY_TYPE_PEX2: |
| 2013 | case PHY_TYPE_PEX3: |
| 2014 | ret = comphy_pcie_power_up( |
| 2015 | lane, pcie_width, ptr_comphy_map->clk_src, |
Stefan Roese | 2313efe | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 2016 | serdes_map->end_point, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2017 | hpipe_base_addr, comphy_base_addr); |
| 2018 | break; |
| 2019 | case PHY_TYPE_SATA0: |
| 2020 | case PHY_TYPE_SATA1: |
| 2021 | case PHY_TYPE_SATA2: |
| 2022 | case PHY_TYPE_SATA3: |
| 2023 | ret = comphy_sata_power_up( |
| 2024 | lane, hpipe_base_addr, comphy_base_addr, |
Rabeeh Khoury | 320bd15 | 2018-09-06 12:37:48 +0300 | [diff] [blame] | 2025 | ptr_chip_cfg->cp_index, |
| 2026 | serdes_map[lane].invert); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2027 | break; |
| 2028 | case PHY_TYPE_USB3_HOST0: |
| 2029 | case PHY_TYPE_USB3_HOST1: |
| 2030 | case PHY_TYPE_USB3_DEVICE: |
| 2031 | ret = comphy_usb3_power_up(lane, hpipe_base_addr, |
| 2032 | comphy_base_addr); |
| 2033 | break; |
| 2034 | case PHY_TYPE_SGMII0: |
| 2035 | case PHY_TYPE_SGMII1: |
| 2036 | case PHY_TYPE_SGMII2: |
| 2037 | case PHY_TYPE_SGMII3: |
| 2038 | if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { |
| 2039 | debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", |
| 2040 | lane); |
| 2041 | ptr_comphy_map->speed = PHY_SPEED_1_25G; |
| 2042 | } |
| 2043 | ret = comphy_sgmii_power_up( |
| 2044 | lane, ptr_comphy_map->speed, hpipe_base_addr, |
| 2045 | comphy_base_addr); |
| 2046 | break; |
Stefan Roese | db720b7 | 2017-04-24 18:45:21 +0300 | [diff] [blame] | 2047 | case PHY_TYPE_SFI: |
| 2048 | ret = comphy_sfi_power_up(lane, hpipe_base_addr, |
Igal Liberman | 989b96f | 2017-04-24 18:45:28 +0300 | [diff] [blame] | 2049 | comphy_base_addr, |
| 2050 | ptr_comphy_map->speed); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2051 | break; |
| 2052 | case PHY_TYPE_RXAUI0: |
| 2053 | case PHY_TYPE_RXAUI1: |
| 2054 | ret = comphy_rxauii_power_up(lane, hpipe_base_addr, |
| 2055 | comphy_base_addr); |
| 2056 | break; |
| 2057 | default: |
| 2058 | debug("Unknown SerDes type, skip initialize SerDes %d\n", |
| 2059 | lane); |
| 2060 | break; |
| 2061 | } |
| 2062 | if (ret == 0) { |
| 2063 | /* |
Stefan Roese | 4fbca01 | 2017-04-24 18:45:25 +0300 | [diff] [blame] | 2064 | * If interface wans't initialized, set the lane to |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2065 | * PHY_TYPE_UNCONNECTED state. |
| 2066 | */ |
| 2067 | ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 2068 | pr_err("PLL is not locked - Failed to initialize lane %d\n", |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2069 | lane); |
| 2070 | } |
| 2071 | } |
| 2072 | |
| 2073 | debug_exit(); |
| 2074 | return 0; |
| 2075 | } |