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git01.mediatek.com / filogic / uboot / 9900db10c91a9c474d6116b325d22c3d353aeb03 / . / board / sunxi / dram_timings_sun4i.h
blob: 29b934da639c86b1830d1e26b7a751b6b227a21a [file] [log] [blame]
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame^]1/* This file is automatically generated, do not edit */
2
3#if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H)
4# if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
5 .cas = 6,
6 .tpr0 = 0x268e5590,
7 .tpr1 = 0xa090,
8 .tpr2 = 0x22a00,
9 .emr2 = 0x0,
10# elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
11 .cas = 6,
12 .tpr0 = 0x288f6690,
13 .tpr1 = 0xa0a0,
14 .tpr2 = 0x22a00,
15 .emr2 = 0x0,
16# elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
17 .cas = 6,
18 .tpr0 = 0x2a8f6690,
19 .tpr1 = 0xa0a0,
20 .tpr2 = 0x22a00,
21 .emr2 = 0x0,
22# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
23 .cas = 7,
24 .tpr0 = 0x2ab06690,
25 .tpr1 = 0xa0a8,
26 .tpr2 = 0x22a00,
27 .emr2 = 0x8,
28# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
29 .cas = 7,
30 .tpr0 = 0x2cb16690,
31 .tpr1 = 0xa0b0,
32 .tpr2 = 0x22e00,
33 .emr2 = 0x8,
34# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
35 .cas = 7,
36 .tpr0 = 0x30b26690,
37 .tpr1 = 0xa0b8,
38 .tpr2 = 0x22e00,
39 .emr2 = 0x8,
40# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
41 .cas = 7,
42 .tpr0 = 0x30b27790,
43 .tpr1 = 0xa0c0,
44 .tpr2 = 0x23200,
45 .emr2 = 0x8,
46# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
47 .cas = 7,
48 .tpr0 = 0x32b27790,
49 .tpr1 = 0xa0c0,
50 .tpr2 = 0x23200,
51 .emr2 = 0x8,
52# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
53 .cas = 7,
54 .tpr0 = 0x34d37790,
55 .tpr1 = 0xa0d0,
56 .tpr2 = 0x23600,
57 .emr2 = 0x8,
58# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
59 .cas = 7,
60 .tpr0 = 0x36d47790,
61 .tpr1 = 0xa0d8,
62 .tpr2 = 0x23600,
63 .emr2 = 0x8,
64# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */
65 .cas = 9,
66 .tpr0 = 0x36b488b4,
67 .tpr1 = 0xa0c8,
68 .tpr2 = 0x2b600,
69 .emr2 = 0x10,
70# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */
71 .cas = 9,
72 .tpr0 = 0x38b488b4,
73 .tpr1 = 0xa0c8,
74 .tpr2 = 0x2ba00,
75 .emr2 = 0x10,
76# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */
77 .cas = 9,
78 .tpr0 = 0x3ab588b4,
79 .tpr1 = 0xa0d0,
80 .tpr2 = 0x2ba00,
81 .emr2 = 0x10,
82# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */
83 .cas = 9,
84 .tpr0 = 0x3cb699b4,
85 .tpr1 = 0xa0d8,
86 .tpr2 = 0x2be00,
87 .emr2 = 0x10,
88# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */
89 .cas = 9,
90 .tpr0 = 0x3eb799b4,
91 .tpr1 = 0xa0e8,
92 .tpr2 = 0x2be00,
93 .emr2 = 0x10,
94# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */
95 .cas = 9,
96 .tpr0 = 0x42b899b4,
97 .tpr1 = 0xa0f0,
98 .tpr2 = 0x2c200,
99 .emr2 = 0x10,
100# else
101# error CONFIG_DRAM_CLK is set too high
102# endif
103#elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J)
104# if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */
105 .cas = 6,
106 .tpr0 = 0x268e6690,
107 .tpr1 = 0xa090,
108 .tpr2 = 0x22a00,
109 .emr2 = 0x0,
110# elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */
111 .cas = 6,
112 .tpr0 = 0x2a8f6690,
113 .tpr1 = 0xa0a0,
114 .tpr2 = 0x22a00,
115 .emr2 = 0x0,
116# elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */
117 .cas = 6,
118 .tpr0 = 0x2a8f6690,
119 .tpr1 = 0xa0a0,
120 .tpr2 = 0x22a00,
121 .emr2 = 0x0,
122# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */
123 .cas = 8,
124 .tpr0 = 0x2cb07790,
125 .tpr1 = 0xa0a8,
126 .tpr2 = 0x22a00,
127 .emr2 = 0x8,
128# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */
129 .cas = 8,
130 .tpr0 = 0x2eb17790,
131 .tpr1 = 0xa0b0,
132 .tpr2 = 0x22e00,
133 .emr2 = 0x8,
134# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */
135 .cas = 8,
136 .tpr0 = 0x30b27790,
137 .tpr1 = 0xa0b8,
138 .tpr2 = 0x22e00,
139 .emr2 = 0x8,
140# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */
141 .cas = 8,
142 .tpr0 = 0x32b28890,
143 .tpr1 = 0xa0c0,
144 .tpr2 = 0x23200,
145 .emr2 = 0x8,
146# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */
147 .cas = 8,
148 .tpr0 = 0x34b28890,
149 .tpr1 = 0xa0c0,
150 .tpr2 = 0x23200,
151 .emr2 = 0x8,
152# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */
153 .cas = 8,
154 .tpr0 = 0x36d38890,
155 .tpr1 = 0xa0d0,
156 .tpr2 = 0x23600,
157 .emr2 = 0x8,
158# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */
159 .cas = 8,
160 .tpr0 = 0x38d48890,
161 .tpr1 = 0xa0d8,
162 .tpr2 = 0x23600,
163 .emr2 = 0x8,
164# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */
165 .cas = 10,
166 .tpr0 = 0x38b499b4,
167 .tpr1 = 0xa0c8,
168 .tpr2 = 0x2b600,
169 .emr2 = 0x10,
170# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */
171 .cas = 10,
172 .tpr0 = 0x3ab499b4,
173 .tpr1 = 0xa0c8,
174 .tpr2 = 0x2ba00,
175 .emr2 = 0x10,
176# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */
177 .cas = 10,
178 .tpr0 = 0x3cb599b4,
179 .tpr1 = 0xa0d0,
180 .tpr2 = 0x2ba00,
181 .emr2 = 0x10,
182# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */
183 .cas = 10,
184 .tpr0 = 0x3eb699b4,
185 .tpr1 = 0xa0d8,
186 .tpr2 = 0x2be00,
187 .emr2 = 0x10,
188# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */
189 .cas = 10,
190 .tpr0 = 0x40b7aab4,
191 .tpr1 = 0xa0e8,
192 .tpr2 = 0x2be00,
193 .emr2 = 0x10,
194# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */
195 .cas = 10,
196 .tpr0 = 0x44b8aab4,
197 .tpr1 = 0xa0f0,
198 .tpr2 = 0x2c200,
199 .emr2 = 0x10,
200# else
201# error CONFIG_DRAM_CLK is set too high
202# endif
203#else
204# error CONFIG_DRAM_TIMINGS_* is not defined
205#endif